Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Jack DiLullo"'
Publikováno v:
Microprocessors and Microsystems. 45:241-252
In a high-speed synthesis design environment, designers struggle to ensure that multi-clock and multi-power interfaces are designed, placed, connected and timed correctly. Identifying and applying proper timing constraints such as "no cycle stealing"
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::79e077d0a1cbc59a570687e8d6b71cfa
https://doi.org/10.1016/j.micpro.2016.05.012
https://doi.org/10.1016/j.micpro.2016.05.012
Autor:
David W. Lewis, Joachim Keinert, R. D. Morel, Jack DiLullo, A. E. Barish, Peter J. Camporese, P. E. Dudley, D. Thomas, Howard H. Smith, J. R. Ripley, R. Berridge, R. Averill, Thomas Edward Rosser, Phillip J. Restle, Michael Alexander Bowen, Nicole Schwartz, Patrick M. Williams, P. Shephard, Steve Runyon
Publikováno v:
IBM Journal of Research and Development. 51:685-714
The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f5bf2c0dccdc2f4f0523c80566f9d43
https://doi.org/10.1147/rd.516.0685
https://doi.org/10.1147/rd.516.0685
Autor:
Gaurav Mittal, Scott A. Taylor, Bradley McCredie, Jack DiLullo, E. Chan, L. Clark, B. Huott, Sam Gat-Shang Chu, Norman Karl James, Y.H. Chan, M. Lanzerotti, J. Ripley, Brian W. Curran, Donald W. Plass, Joshua Friedrich, Hung Le, Eric Fluhr
Publikováno v:
ISSCC
The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microproces
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::587a6002500c60fc57234643110e1bd5
https://doi.org/10.1109/isscc.2007.373605
https://doi.org/10.1109/isscc.2007.373605
Autor:
J. Dawson, Mike Lee, S. Dodson, Phillip J. Restle, Balaram Sinharoy, G. Gorman, N. Schwartz, Steve Runyon, Ronald Nick Kalla, Joachim Gerhard Clabes, M. Goulet, Jack DiLullo, J. Wagoner, Mark D. Sweet, L. Powell, Paul H. Muench, J. McGill, Donald W. Plass, Michael Stephen Floyd, Joshua Friedrich, Sam Gat-Shang Chu
Publikováno v:
2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).
POWER5/sup TM/ is the next generation of IBM's POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d86faeb3de9bea64e836b981ea22aa56
https://doi.org/10.1109/icicdt.2004.1309931
https://doi.org/10.1109/icicdt.2004.1309931
Autor:
Joachim Gerhard Clabes, Michael Normand Goulet, Mark D. Sweet, Donald W. Plass, Balaram Sinharoy, Gary Alan Gorman, Ronald Nick Kalla, Steve Runyon, Larry Powell, Phillip J. Restle, Joseph McGill, Mike Lee, Paul H. Muench, James Donald Wagoner, James W. Dawson, Michael Stephen Floyd, Jack DiLullo, Steve Dodson, Nicole Schwartz, Joshua Friedrich, Sam Gat-Shang Chu
Publikováno v:
DAC
POWER5 offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support. The 276M transistor processor is implemented in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::94b0caf8594f41be065ac17fa88f5928
https://doi.org/10.1145/996566.996749
https://doi.org/10.1145/996566.996749
Autor:
John George Petrovick, Jack DiLullo, Carl J. Anderson, J. Keaty, Joachim Gerhard Clabes, Shao-Fu S. Chu, P. E. Dudley, James D. Warnock, J. Wagoner, G. Nussbaum, S. Weitzel, B. A. Zoric, R. Weiss, G. Plum, Steve Runyon, Byron L. Krauter, Bradley McCredie, Pong-Fei Lu, S. Schmidt, Michael R. Scheuermann, Phillip J. Restle, Craig R. Carter, J. LeBlanc, J.M. Tendier, P. Harvey
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dad8d8143abf2e20d495527032da1d11
https://doi.org/10.1109/isscc.2001.912617
https://doi.org/10.1109/isscc.2001.912617
Autor:
Stephen Douglas Posluszny, Frank J. Musante, Michael A. Kazda, Joshua Friedrich, Lakshmi Reddy, Vasant Rao, Douglass T. Lamb, Jeremy T. Hopkins, Gustavo E. Tellez, Cliff Sze, Markus J. Buehler, Uwe Brandt, Benjamin R. Russell, Thomas Edward Rosser, Zahi M. Kurzum, Jack DiLullo, Jens Noack, Ruchir Puri, Haifeng Qian, Peter J. Osler, Alice Lee, Joachim Keinert, Shyam Ramji, Haoxing Ren, Mozammel Hossain
Publikováno v:
IBM Journal of Research and Development. 55:9:1-9:14
The IBM POWER7® microprocessor, which is the next-generation IBM POWER® processor, leverages IBM's 45-nm silicon-on-insulator (SOI) process with embedded dynamic random access memory to achieve industry-leading performance. To deliver this complex
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1db78a9d665e493366d1cce9d5d51b3b
https://doi.org/10.1147/jrd.2011.2105692
https://doi.org/10.1147/jrd.2011.2105692