Zobrazeno 1 - 10
of 53
pro vyhledávání: '"Ja-Chun Ku"'
Autor:
Hyun Sun Lee, Tae Jung Ha, Hoe Gwon Jung, Yoocharn Jeon, Sung Joo Hong, Kyu Sung Kim, Suock Chung, Wan Gee Kim, Hyeong Soo Kim, Lee Jung Hoon, Gary Gibson, Eung Rim Hwang, Jong Hee Yoo, Kyung Wan Kim, Kee Jeung Lee, Soo Gil Kim, Suk Pyo Song, Hyojin Kim, Seonghyun Kim, Ja Chun Ku, Jong Il Kim, Jong Chul Lee, Sang Hoon Cho, Jae-yeon Lee, Jong Ho Song, Jong Ho Kang, Beom-Yong Kim, Jung Ho Shin, Yong Taek Park
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM).
In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:1323-1336
Aggressive technology scaling down and low-power design techniques lead to uneven distributed power density, which translates into heat flow in the chips, causing significant temperature variations in both spatial and temporal terms. In order to miti
Autor:
Ja-Chun Ku, Seung Joon Jeon, Seung-Woo Do, Jae-Geun Oh, Jin-Ku Lee, Seong Ho Kong, Min-Ae Ju, Yong-Hyun Lee
Publikováno v:
Journal of the Korean Physical Society. 55:1065-1069
A plasma-doping (PLAD) process utilizing a PH3 plasma is presented to fabricate a n /p ultrashallow junction at room temperature. When PLAD is completed, an excimer laser annealing (ELA) process is performed using an ArF (193 nm) excimer laser with p
Autor:
Sivakumar Venkat, Ja-Chun Ku, Yong Shin, Carlotte Douglas, Scott Seo, SungKi Park, Jason Saito, Byeong-Sam Moon, KeunSu Kim, William Shen, Jeong-Hoon An, Hyo Sik Suh, Jonggeun Park, Jiae Kim, Sanghyun Lee
Publikováno v:
ECS Transactions. 16:321-329
This paper talks about a new class of yield impacting defect types known as polishing induced defects (PID) on polished silicon substrates. These defects were found to cause significant yield drop associated with a pump bias failure in the sub-60nm f
Autor:
Yong Soo Kim, Kwan-Yong Lim, Se Aug Jang, Min Gyu Sung, Hong-Seon Yang, Jinwoong Kim, Heung-Jae Cho, Yun Taek Hwang, Ja Chun Ku
Publikováno v:
Japanese Journal of Applied Physics. 47:2704-2709
We investigated the effect of boron at the interface of the diffusion barrier in tungsten polymetal gate stacks on the gate contact interfacial resistance between tungsten and p+ polycrystalline silicon (poly-Si). B–N formation can occur at the bot
Autor:
Yehea Ismail, Ja Chun Ku
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27:241-248
Traditionally, the minimum possible area of a very large scale integration (VLSI) layout is considered to be the best for delay and power minimization due to decreased interconnect capacitance. This paper, however, shows that the use of minimum area
Autor:
Seung Ryong Lee, Se-Aug Jang, Ja-Chun Ku, Hong-Seon Yang, Min Gyu Sung, Heung-Jae Cho, Kwan-Yong Lim, Tae-Yoon Kim, Yong Soo Kim, Jinwoong Kim
Publikováno v:
Japanese Journal of Applied Physics. 46:7256-7262
Gate oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) gate stack were investigated in detail. The insertion of a thin WSix layer in a tungsten poly gate stack could effectivel
Autor:
Ja Chun Ku, Yehea Ismail
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:1882-1888
With ever increasing power density and temperature variations within chips, it is very important to correctly model temperature effects on the devices in a compact way and to predict their scaling. In this paper, it is first shown that the temperatur
Autor:
Ja Chun Ku, Yehea Ismail
Publikováno v:
ISLPED
In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is pre
Publikováno v:
MICRO
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can be suboptimal when thermal effects are considered. Then, we propose a th