Výsledky vyhledávání - "JUNPEI, INOUE"

Optimization Methodology of Layer Numbers with Circuit/Process Co-Design

Autor: Junpei Inoue, Hidenari Nakashima, Kazuya Masu, Takumi Uezono, Takanori Kyogoku, Kenichi Okada

Publikováno v: Japanese Journal of Applied Physics. 45:2476-2480

The number of layers directly affects manufacturing cost, and it also has a trade-off with the circuit area in multilevel interconnection LSI. In this paper, we propose a co-design methodology for circuits and processes to optimize the number of inte

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6e0a255e5784a85117af34efa0b4f91d
https://doi.org/10.1143/jjap.45.2476

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Wire Length Distribution Model for System LSI

Autor: Takanori Kyogoku, Kazuya Masu, Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Takumi Uezono

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3445-3452

This paper concerns a new model for estimating the wire length distribution (WLD) of a system-on-a-chip (SoC). The WLD represents the correlation between wire length and the number of interconnects, and we can predict circuit performances such as pow

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2afae2606b9fce899e7dcb352a83998f
https://doi.org/10.1093/ietfec/e88-a.12.3445

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Evaluation of X Architecture Using Interconnect Length Distribution

Autor: Naohiro Takagi, Hidenari Nakashima, Kazuya Masu, Kenichi Okada, Junpei Inoue

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3437-3444

In this paper, we propose a new Interconnect Length Distribution (ILD) model to evaluate X architecture. X architecture uses 45°-wire orientations in addition to 90°-wire orientations, which contributes to reduce the total wire length and the numbe

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1eb04fa1286f90616063a3c075db866b
https://doi.org/10.1093/ietfec/e88-a.12.3437

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Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model

Autor: Hidenari Nakashima, Kazuya Masu, Junpei Inoue, Kenichi Okada

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3358-3366

Interconnect Length Distribution (ILD) represents the correlation between the number of interconnects and their length. The ILD can predict power consumption, clock frequency, chip size, etc. High core utilization and small circuit area have been rep

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1ee9a134a1cb62c38845b9b9e56b3583
https://doi.org/10.1093/ietfec/e88-a.12.3358

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Prediction of Delay Time for Future LSI Using On-Chip Transmission Line Interconnects

Autor: Kenichi Okada, Takanori Kyogoku, Kazuya Masu, Takumi Uezono, Junpei Inoue

Publikováno v: SLIP

An on-chip transmission-line interconnect has been proposed to reduce the delay time and power consumption. Transmission lines are used to replace long RC interconnects, and can greatly improve circuit performance. In this work, we estimate the perfo

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4607e800cbba49ea08e329b3cbc8dfc3
http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100397551

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Evaluation of On-Chip Transmission Line Interconnect Using Wire Length Distribution

Autor: Takanori Kyogoku, Kazuya Masu, Junpei Inoue, Shinichiro Gomi, Kenichi Okada, Takumi Uezono, Hiroyuki Ito

Publikováno v: ASP-DAC

On-chip transmission-line interconnect has been proposed to reduce delay time and power consumption. The transmission line is used to replace long RC interconnects. This paper proposes the methodology to replace RC lines with transmission lines, whic

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4a3cbb9faa435ab914067a216b3ae0f5
http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100397549

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Fabrication of Multiple and Tapered Nozzle Holes for Diesel Engines by High-Speed Centrifugal Compaction Combined with Three-Dimensional Printed Cores, Part 1 - Development of Process

Autor: Junpei Inoue, Hiroyuki Y. Suzuki

Publikováno v: The Proceedings of Mechanical Engineering Congress, Japan. 2016:S0410104

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6279df76f51e5da160247cbbddeda9e8
https://doi.org/10.1299/jsmemecj.2016.s0410104

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Optimization methodology of global interconnect structure

Autor: Kenichi Okada, Takumi Uezono, Hidenari Nakashima, Junpei Inoue, Takanori Kyogoku, Kazuya Masu

Publikováno v: ResearcherID

The optimal interconnect structure is required because circuit performance depends on resistance and capacitance in interconnects. This paper proposes the optimization methodology of interconnect structure based on the wire length distribution (WLD)

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ac8bce585dbbc6e881d037364b7744a6
https://doi.org/10.1109/icm.2004.1434584

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Wire Length Distribution Model Considering Core Utilization for System on Chip

Autor: Kazuya Masu, Takanori Kyogoku, Kenichi Okada, Hidenari Nakashima, Takumi Uezono, Junpei Inoue

Publikováno v: ISVLSI

This paper presents a new model to estimate wire length distribution (WLD) of system on chip (SoC). The WLD represents a correlation between wire length and the number of interconnect, and we can predict power consumption, maximum clock frequency, ch

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4862e194f680e405a74e34a7b372002b
https://doi.org/10.1109/isvlsi.2005.76

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