Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution

Autor: Armen Kteyan, Valeriy Sukharev, Alexander Volkov, Jun Ho Choy, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Stephane Moreau

Publikováno v: ISPD '23: Proceedings of the 2023 International Symposium on Physical Design
ISPD'23-International Symposium on Physical Design
ISPD'23-International Symposium on Physical Design, Mar 2023, Virtual event USA, United States. pp.124-132

International audience; A recently proposed methodology for electromigration (EM) assessment in on-chip power/ground grid of integrated circuits has been validated by means of measurements, performed on dedicated test grids. IR drop degradation in th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4c87e664502295538e2be9edfcb68855
https://doi.org/10.1145/3569052.3578922

(Invited, Digital Presentation) Advanced Methodology for Assessing Chip Package Interaction Induced Stress Effects on Chip Performance and Reliability

Autor: JUN-HO Choy, Valeriy Sukharev, Armen Kteyan, Stephane Moreau, Catherine Brunet-Manquat

Publikováno v: ECS Meeting Abstracts. :846-846

In IC industry, the use of multiple die stack packaging has emerged to meet the increasing demand in miniaturization and improved functionality of mobile devices. During chip operation, transistor power dissipation raises temperature unevenly across

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::80c3c78c1e711ac9e56d4d2eb89a157e
https://doi.org/10.1149/ma2022-0217846mtgabs

Assesment of CPI Stress Impact on IC Reliability and Performance in 2.5D/3D Packages

Autor: Armen Kteyan, H. Hovsepyan, Valeriy Sukharev, Jun-Ho Choy

Publikováno v: IRPS

A novel approach to assessing the effects of CPI-induced stresses on performance and durability of ICs with 2.5D/3D chip architectures is presented. It combines the physics-based stress modeling methodology with the capabilities of layout analysis an

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7107d3faeff39cd2631a1dd835e6e8d8
https://doi.org/10.1109/irps.2019.8720471

Electromigration assessment for power grid networks considering temperature and thermal stress effects

Autor: Marko Chew, Xin Huang, Sheldon X.-D. Tan, Jun-Ho Choy, Valeriy Sukharev, Taeyoung Kim

Publikováno v: Integration. 55:307-315

With technology scaling, reliability has emerged as a major design constraint for very-large-scale integrated circuits. Many prior works have investigated electromigration (EM) on full-chip power grid interconnects. However, most of the published res

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6a48d0bda6b377f3dbd1d1effb04296a
https://doi.org/10.1016/j.vlsi.2016.04.001

Finite-difference methodology for full-chip electromigration analysis applied to 3D IC test structure: Simulation vs. experiment

Autor: Stephane Moreau, Jun-Ho Choy, Valeriy Sukharev, Sandeep Chatterjee, Armen Kteyan, Farid N. Najm

Publikováno v: 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

A novel electromigration (EM) assessment method based on a finite-difference (FD) approach has been implemented to study EM degradation in 3D integrated circuit (IC) supply current ports. A dual damascene copper through-silicon via (TSV) based EM tes

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3eb1c4a809bb8675920bb8a2f749c489
https://doi.org/10.23919/sispad.2017.8085259