Zobrazeno 1 - 10
of 203
pro vyhledávání: '"JEDEC memory standards"'
Publikováno v:
2021 22nd International Conference on Electronic Packaging Technology (ICEPT).
The reliability of electronic packaging is one of the most concerned issues, and the board-level drop test has become a key qualification test for assessing the impact reliability of electronic components. In literature, lots of work focus on PCB vib
Publikováno v:
2021 23rd European Microelectronics and Packaging Conference & Exhibition (EMPC).
One of the most challenging aspects of processing electronic parts is the abundance of influencing factors. These have a significant impact on the quality of the finished product. Particularly the affinity to embed moisture in the plastic matrix can
Autor:
Sunil Gupta
Publikováno v:
2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium.
SI (Signal Integrity) analysis of a LPDDR5 SoC-DRAM PoP (Package-on-Package) system using 1-tap DFE (Decision Feedback Equalization) is presented. The system was running at 6.4 Gbps with 0.47V VDDQ at SS corner. The DFE mitigates the reflection based
Publikováno v:
2021 20th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm).
This paper focuses on feature vector identification and prognostics of failure for SAC305 solder PCB’s under varying conditions of shock loads. The test board is a multilayer FR4 of the JEDEC standard dimension with twelve packages arranged in a re
Publikováno v:
2021 China Semiconductor Technology International Conference (CSTIC).
The reliability problem of domestic self-developed chips restricts the wide application of electronic products. Most reliability problems are caused by stress, including residual stress before and after encapsulation and stress introduced during the
Autor:
H. Yoon, Vinayak Bharat Naik, J. Kwon, K. Yamane, L. Pu, J. H. Lim, S. T. Woo, O. Kallensee, J. Hwang, Y. S. You, S. Ong, Jeff J. Xu, L. Zhang, Tae Young Lee, S. H. Jang, S. K L. C. Goh, F. Tan, Eng Huat Toh, D. Zeng, N. Balasankaran, Soh Yun Siah, Hemant Dixit, T. H. Chan, N. L. Chung, R. Low, G. Congedo, R. Chao, Y. Otani, Johannes Mueller, C.G. Lee, T. Merbeth, J. W. Ting, L. Y. Hau, K. W. Gan, Y. Huang, A. Vogel, E. Quek, C. Chiang, Behtash Behin-Aein, W. P. Neo, T. Ling, V. Kriegerstein, Chim Seng Seet, Jen Shuang Wong, B. Pfefferling
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
We demonstrate highly reliable and mass-production ready 22nm FD-SOI 40Mb embedded-MRAM for industrial-grade (-40~125°C) applications. This technology having 5x solder reflows compatibility stack has passed JEDEC standard qualification (ECC-OFF) wit
Publikováno v:
ISCAS
This paper presents an evaluation of the new JEDEC standard JEP173. The JEP173 establishes a characterization procedure to reliably assess the dynamic ON-resistance of GaN lateral power transistors. DC and pulsed measurement setups were developed to
Publikováno v:
2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).
Optical measurement techniques are commonly used in order to inspect the thermal warpage behavior and the deformation of packages during reflow. JEDEC standard has offered four types of methods to measure the warpage: Confocal, Digital Image Correlat
Publikováno v:
2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm).
This paper focusses on the prognostics of damage for a PCB under varying conditions of shock loads. The test board is a multilayer FR4 of JEDEC standard JESD22-B111 specified dimension with 12 packages that are arranged in a rectangular pattern. Heal
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
Board level drop impact tests to evaluate electronic package mounts on printed circuit board (PCB) solder joint reliability is critical, especially for handheld and mobile consumer products. Standard drop tests refer the JEDEC specification (JESD22-B