Zobrazeno 1 - 10
of 238
pro vyhledávání: '"J.Y.-C. Sun"'
Autor:
Kai Shin Li, Yu Shen Yen, J.Y.-C. Sun, Huan Chi Shih, Jeng Hua Wei, Pang Chun Liu, Ya Jui Tsou, Wei-Jen Chen, Denny Duan-Lee Tang, Chee-Wee Liu, Chih-Huang Lai, Jia Min Shieh
Publikováno v:
IEEE Transactions on Electron Devices. 68:6623-6628
A back-end-of-line compatible 400 °C thermally robust perpendicular spin-orbit torque magnetic tunnel junction (p-SOT-MTJ) memory cell with a tunnel magnetoresistance ratio of 130% is demonstrated. It features an energy-efficient spin-transfer-torqu
Autor:
C. T. Wang, Victor C. Y. Chang, Sai Qian Zhang, M. F. Chen, J.Y.-C. Sun, Chih-Hua Chen, Hsiang-Tsung Kung, Jin Cai, Douglas Yu, Bradley McDanel
Publikováno v:
ISCAS
We present a building block architecture for systolic array 3D-IC implementations of convolutional neural network (CNN) inference. The building block can be part of a library offered by a chip design service provider to support efficient CNN implemen
Autor:
J.Y.-C. Sun
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
Wafer based 3D×3D system scaling revolutionizes machine learning (ML) and artificial intelligence (AI) as well as mobile computing. It may trigger a big bang in intelligent ubiquitous computing. 3D CMOS scaling continues with many challenges and opp
Publikováno v:
IEEE Transactions on Electron Devices. 60:1814-1819
This paper analyzes the 2-D short-channel effect in ultrathin SOI MOSFETs. An empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices. We show how this scale length is re
Akademický článek
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Autor:
J.Y.-C. Sun
Publikováno v:
A-SSCC
Semiconductor innovation through a new paradigm of 3D×3D System Scaling can carry the industry into the next decade. Besides the internet of things (IoT), cloud computing, and big data analytics, we can imagine a bionic age emerging with digitally-e
Publikováno v:
IEEE Transactions on Electron Devices. 52:1324-1334
A high quality 90-nm CMOS-based technology portfolio suitable for various RF IC applications is presented. The portfolio is built up by a wide selection of active and passive components and a user-friendly process design kit (PDK). Layout-optimized R
Autor:
J.Y.-C. Sun, Yung Shun Chen, Shien Yang Wu, Chih Ping Chao, Bi Shiou Chiou, Chin Yuan Ko, Yee Chaung See, Ming Hsung Chang, Kuo Hua Lee, Hung Der Su
Publikováno v:
Japanese Journal of Applied Physics. 42:7232-7237
The breakdown detections of ultrathin oxide (1.4–2 nm) using a fast voltage ramp have been studied. It was found that the breakdown voltage test of deep sub-micron technology requires the reduction of the gate area of test patterns and therefore th
Autor:
J.Y.-C. Sun, Yung Shun Chen, Hung Der Su, Yee Chaung See, Ming Hsung Chang, Chih Ping Chao, Kuo Hua Lee, Bi Shiou Chiou, Shien Yang Wu
Publikováno v:
Japanese Journal of Applied Physics. 42:5521-5526
The oxide breakdown characteristics of ultrathin oxide (2.2 nm) have been studied in this paper. Light emission microscopy (EMMI) analysis shows that each breakdown has a specific failure location with a random distribution. Gate leakage current incr
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:444-449
Several physical phenomena in highly scaled CMOS technology have now become first-order elements affecting the electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-e