Výsledky vyhledávání - "J.W Weijtmans"

Factors Influencing the Leakage Current in Embedded SiGe Source/Drain Junctions

Autor: Hugo Bender, Roger Loo, J.P. Lu, Andriy Hikavyy, B. Vissouvanadin, Vladimir Machkaoutsan, Mohammad Kamruzzaman Chowdhury, Peter Verheyen, Pierre Tomasini, Cor Claeys, S.G Thomas, Eddy Simoen, R. Wise, J.W. Weijtmans, Mireia Bargallo Gonzalez

Publikováno v: IEEE Transactions on Electron Devices. 55:925-930

This paper studies the leakage current components in embedded Si1-x,Gex, source/drain (S/D) p+-n junctions, with different Ge contents, varying between 20% and 35%. In addition, the impact of performing a highly doped drain (HDD) implantation before

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bb2850a9a8ebe1bcb28e47173969a343
https://doi.org/10.1109/ted.2007.914843

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Influence of the Highly-Doped Drain Implantation and the Window Size on Defect Creation in p+/n Si1-XGex Source/Drain Junctions

Autor: S.G Thomas, Cor Claeys, J. Geypen, Hugo Bender, M. Kamruzzaman Chowdhury, Nada Bhouri, Eddy Simoen, Peter Verheyen, Olivier Richard, Pierre Tomasini, B. Vissouvanadin, V. Machkaoutsan, J.P. Lu, Roger Loo, R. Wise, J.W. Weijtmans, Mireia Bargallo Gonzalez, H. Hikavyy

Publikováno v: Solid State Phenomena. :95-100

This paper presents an investigation of the impact of a Highly Doped Drain (HDD) implantation after epitaxial deposition on Si1-xGex S/D junction characteristics. While the no HDD diodes exhibit the usual scaling of the leakage current density with P

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::08bdb78a7eeac2a117690a9c17a68a75
https://doi.org/10.4028/www.scientific.net/ssp.131-133.95

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Analysis of the Pre-epi Bake Conditions on the Defect Creation in Recessed SiGe S/D Junctions

Autor: Peter Verheyen, Andriy Hikavyy, Bertrand Vissouvanadin Soubaretty, Yasutoshi Okuno, Frederik Leys, Pierre Tomasini, R. Wise, Vladimir Machkaoutsan, Luc Geenen, Roger Loo, C. Claeys, Benny Van Daele, J.P. Lu, J.W. Weijtmans, Shawn G. Thomas, Nicole Thomas, Eddy Simoen, Mireia Bargallo Gonzalez

Publikováno v: ECS Transactions. 11:47-53

This paper reports on the impact of the pre-epi bake conditions on the epitaxial growth of Si1 xGex Source-Drain (S/D) stressors as studied by p-n junction leakage analysis. It has been demonstrated that the presence of impurity-related (O, C) defect

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::54650f1444a348e7aece96b5fd1d4eb5
https://doi.org/10.1149/1.2778649

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Relaxation-Induced Excess Leakage Current in Recessed Si1-xGex Source/Drain Junctions

Autor: Frederik Leys, Shawn G. Thomas, R. Wise, Roger Loo, J.W. Weijtmans, Nada Bhouri, Cor Claeys, Peter Verheyen, Vladimir Machkaoutsan, J.P. Lu, Eddy Simoen, Pierre Tomasini, Mireia Bargallo Gonzalez, Olivier Richard, Mohammad Kamruzzaman Chowdhury

Publikováno v: ECS Transactions. 6:389-396

This paper presents an investigation of the effect of the relaxation on the electrical performance of recessed Si1-xGex source/drain junctions. It is shown, that the peripheral leakage current density scales exponentially with the total epilayer thic

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::13bd7ebc222cf4ee6fb900b94264d4a3
https://doi.org/10.1149/1.2727424

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Probing Nanoscale Local Lattice Strains in Advanced Si CMOS Devices by CBED: A Tutorial with Recent Results

Autor: Jiang Huang, Moon J. Kim, Elisabeth Marley Koontz, J.W. Weijtmans, R.B. Irwin, Yuguo Wang, P.J. Jones, P.R. Chidambaram, S. Tang, Rick L. Wise

Publikováno v: ECS Transactions. 2:541-547

The experimental methodology to characterize the nanoscale local lattice strain in advanced Si CMOS devices by using Focused Ion Beam (FIB) system and Convergent Beam Electron Diffraction (CBED) is discussed. Through both high spatial resolution of T

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e918ad1d89dd0a1f40ebd7e061487b71
https://doi.org/10.1149/1.2195689

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PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology

Publikováno v: Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and le

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::256c3a19fe8287f31557b297e4fd71aa
https://doi.org/10.1109/vlsi-tsa.2012.6210152

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High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor

Publikováno v: 2008 IEEE International Electron Devices Meeting.

For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET wi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4be978b7620a3fb60241f50d73353f21
https://doi.org/10.1109/iedm.2008.4796611

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On implementation of embedded phosphorus-doped SiC stressors in SOI nMOSFETs

Publikováno v: 2008 Symposium on VLSI Technology.

We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a subst

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2f3d6433d08c3448170edcdeea296418
https://doi.org/10.1109/vlsit.2008.4588607

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