Zobrazeno 1 - 10
of 55
pro vyhledávání: '"J.T. Clemens"'
Publikováno v:
IEEE Electron Device Letters. 21:227-229
We have found that nitrogen incorporation in the gate-oxide, by implantation into the Si, degrades the low field inversion mobility. Although submicron transistors fabricated using nitrogen implantation have been reported to show higher drive current
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d5bb8a3f78f7622b3d36a7f86a8fb68
https://doi.org/10.1109/55.841304
https://doi.org/10.1109/55.841304
Autor:
J.T. Clemens
Publikováno v:
Sixth Biennial IEEE-USA Careers Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f415f1a1a6f45fbf69d47bbf8d6298f7
https://doi.org/10.1109/career.1989.643495
https://doi.org/10.1109/career.1989.643495
Autor:
J.I. Colonell, Frieder H. Baumann, C.P. Chang, E.J. Lloyd, H. Vaidya, C.S. Pai, K.P. Cheung, R. Liu, J.T. Clemens, C.T. Liu, A. Ghetti, J.F. Miner, W.Y.C. Lai, H.-H. Vuong
Publikováno v:
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
In the fabrication of CMOS devices with sub-3 nm gate oxides, we have observed severe variation of the oxide thickness (t/sub ox/). For devices with 2.5 nm t/sub ox/ at the center of the channel, the physical t/sub ox/ ranges from 1.8 nm to 4.2 nm at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eefe0b14a1b0766b04aedaaede5fb8c9
https://doi.org/10.1109/vlsit.1999.799347
https://doi.org/10.1109/vlsit.1999.799347
Autor:
J.T. Clemens, C.-S. Pai, C.T. Liu, W.Y.C. Lai, Hem M. Vaidya, C.-P. Chang, J.I. Colonell, R. Liu, K.P. Cheung, J.F. Miner, E. Hasegawa
Publikováno v:
1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).
We have found that the total trapped negative charge in a thin gate-oxide at the point of breakdown is a strong function of the stress field. This observation is in direct contrast with previous reports in the literature. The field dependent behavior
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6463b6eedec469224f259fd6ecf95415
https://doi.org/10.1109/relphy.1999.761592
https://doi.org/10.1109/relphy.1999.761592
Autor:
R. Dail, Stephen C. Kuehne, S.F. Shive, J.I. Colonell, J.T. Clemens, H. Vaidya, C.S. Pai, R. Liu, H.-H. Vuong, E.J. Lloyd, C.P. Chang, K.P. Cheung, M. Bude, W.Y.C. Lai, C.T. Liu, M.A. Abdelgadir, Y. Ma, J.F. Miner, Frieder H. Baumann
Publikováno v:
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
Shallow trench isolation (STI) has become the standard isolation structure for sub-micron silicon CMOS technologies (Perera et al, 1995; Chatterjee et al, 1996). However, following the trend of device scaling, isolation for future device generations
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2c9cdab7d40b4a0640581dca2a7a173
https://doi.org/10.1109/vlsit.1999.799393
https://doi.org/10.1109/vlsit.1999.799393
Autor:
J.I. Colonell, Hem M. Vaidya, K.P. Cheung, Qiang Lu, C.-P. Chang, W.Y.C. Lai, N.A. Ciampa, R. Liu, J.F. Miner, J.T. Clemens, C.-S. Pai, C.T. Liu
Publikováno v:
1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).
A number of groups have reported that the stress-induced leakage current (SILC) follows a power law dependence on the stress time. In this study, we observed that the power-law behaviour is only an approximation of the fast rising part of a more comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2377c7a052da1e3cc149bceb2c08c489
https://doi.org/10.1109/relphy.1999.761645
https://doi.org/10.1109/relphy.1999.761645
Autor:
W.Y.C. Lai, T. Kook, Hem M. Vaidya, S.F. Shive, C.-P. Chang, R. Liu, C.-S. Pai, C.T. Liu, J.T. Clemens, K.G. Steiner, K.P. Cheung, J.I. Colonell
Publikováno v:
1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100).
Recently, there has been strong interest in using the surface potential measurement (SPM) method to monitor plasma charging damage. This method is also called contact potential measurement (CPM). The appeal of this method is obvious, in that it is fa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd458096241f7797a372253f5ed46285
https://doi.org/10.1109/ppid.1998.725564
https://doi.org/10.1109/ppid.1998.725564
Autor:
J.T. Clemens, W.Y.C. Lai, C.-P. Chang, R. Liu, C.-S. Pai, E. Hasegawa, J.I. Colonell, Hem M. Vaidya, C.T. Liu, K.P. Cheung
Publikováno v:
1998 3rd International Symposium on Plasma Process-Induced Damage (Cat. No.98EX100).
The question of whether or not thinner gate oxide is less susceptible to plasma charging damage depends on a number of factors. One important factor is the definition of damage itself. The measurement method is linked to the definition of damage. Whe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::700f81d74828469bf2271fa36a19d388
https://doi.org/10.1109/ppid.1998.725568
https://doi.org/10.1109/ppid.1998.725568
Autor:
R. Liu, C.P. Chang, J.T. Clemens, W.Y.C. Lai, H. Vaidya, C.S. Pai, J.I. Colonell, C.T. Liu, Conor S. Rafferty, K.P. Cheung
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
Boron diffusion from p/sup +/-poly gate through thin gate oxide not only causes a transistor to degrade, but also reduces the reliability of the thin gate-oxide. This problem has been studied extensively. Since high concentration of boron is used in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5eaab54ff04fc46e89de0bcd563a1489
https://doi.org/10.1109/vlsit.1998.689255
https://doi.org/10.1109/vlsit.1998.689255
Autor:
J.T. Clemens, J. T. C. Lee, C. Gruensfelder, W.W. Tai, J. Frackoviak, W.Y.C. Lai, F.P. Klemens, Dale C. Jacobson, O. Nalamasu, H. Vaidya, C.S. Pai, William M. Mansfield, C.P. Chang, K. Bolan, Stephen C. Kuehne, R. Liu, M. Frei, H.L. Maynard, H.-H. Vuong, M.J. Thoma, K.P. Cheung, D.M. Boulin, Allen G. Timko, P. J. Silverman, C.T. Liu, Steven James Hillenius, J.I. Colonell, Joze Bevk, D. Monroe, R.W. Key, G.P. Watson, R. Santiesteban, Gerhard Hobler, M. Oh, Raymond A. Cirelli
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
Summary form only given. We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget for gate activation, made possibl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb6dd278f2675a7adc2617463a3c98c8
https://doi.org/10.1109/vlsit.1998.689205
https://doi.org/10.1109/vlsit.1998.689205