Zobrazeno 1 - 10
of 26
pro vyhledávání: '"J.R. Yeargain"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 28:371-374
A simple BiCMOS configuration employing the source-well tie PMOS/n-p-n pull-down combination is proposed for low-voltage, high-performance operations. The improved BiCMOS gate delay time over that of the NMOS/n-p-n (conventional) BiCMOS gate is confi
Autor:
R. Bertram, P.G.Y. Tsui, B. Pappert, F. Pintchovski, S.W. Sun, J.R. Yeargain, Jeffrey L. Klein, B.M. Somero
Publikováno v:
IEEE Transactions on Electron Devices. 39:2733-2739
A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5- mu m microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p
Publikováno v:
Proceedings of the IEEE Custom Integrated Circuits Conference.
A BiCMOS technology, suitable for low voltage application, was developed for 0.5 pm logic products. This modular BiCMOS technology is based on a single poly, triple level metal CMOS process with the addition of vertical polysilicon NPN and substrate
Publikováno v:
27th Annual Proceedings., International Reliability Physics Symposium.
Publikováno v:
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.
An advanced high-voltage CMOS process has been developed for custom products with on-chip electrically erasable programmable read-only memory (EEPROM). The minimum feature size is 1.2 mu m. Process adjustments to achieve >18-V high-voltage operation
Autor:
Kuo-Tung Chang, Craig T. Swift, J.R. Yeargain, Danny Pak-Chum Shum, J.M. Higman, William J. Taylor, Ko-Min Chang
Publikováno v:
Proceedings of 1994 IEEE International Electron Devices Meeting.
A new low current two-step erasing scheme for "repairing" over-erased flash EEPROM cells has been developed. The cell convergence is achieved with 10 V on the control gate and 5 V on the source and drain for 50 ms. The convergence current is kept to
Autor:
S.W. Sun, B. Pappert, J.R. Yeargain, P.G.Y. Tsui, Jeffrey L. Klein, F. Pintchovski, B.M. Somero
Publikováno v:
International Electron Devices Meeting 1991 [Technical Digest].
A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5 mu m logic and microprocessor products. Both the poly-emitter vertical n-p-n a
Autor:
David W. Chrudimsky, H. Choe, Clinton C. K. Kuo, Ko-Min Chang, B. Morton, M. Bowers, Philip J. Tobin, Yoshio Okada, Y.-S. Kim, J.R. Yeargain, S.A. Ajuria
Publikováno v:
IEEE Electron Device Letters. 14:342-344
The superior characteristics of floating-gate electron tunneling MOS (FETMOS) EEPROMs fabricated using a furnace N/sub 2/O oxynitridation process are described. These devices exhibited about eight times better endurance and good data retention charac
Publikováno v:
IEEE Transactions on Electron Devices. 36:2422-2432
A novel salicided twin-tub 0.5- mu m CMOS process using germanium implantation is presented. n/sup +/ and p/sup +/ dopants are implanted after salicide formation to fabricate devices with low junction leakage and low silicide-to-diffusion contact res
Publikováno v:
IEEE Electron Device Letters. 9:293-295
The uniformity of Ti silicide resistance has been greatly improved by using an ion-beam mixing technique. The integrity of both MOS capacitors and p-n junction diodes has been improved. N-channel MOS field-effect transistors fabricated with this tech