Zobrazeno 1 - 10
of 68
pro vyhledávání: '"J.R. Pfiester"'
Publikováno v:
IEEE Transactions on Electron Devices. 41:228-232
The electrical properties of polycrystalline silicon-germanium (poly-Si/sub 1/spl minus/x/Ge/sub x/) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P/sup +/)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::863ecc8ff6c00074c9be83d0df28945f
https://doi.org/10.1109/16.277374
https://doi.org/10.1109/16.277374
Autor:
J.R. Pfiester, Alvin Leng Sun Loke, G.W. Motley, A.M. Volz, Robert K. Barnes, T.E. Cynkar, R.R. Kennedy, R.A. Zimmer, M.J. Gilsdorf, D.A. Hood, E.J. Rojas, K.L. Arave, T.M. Walley, Michael M. Oshima, J.O. Barnes, R.H. Miller, Charles E. Moore, H.H.M. Pang, T.T. Wee, R.J. Martin
Publikováno v:
CICC
A low-jitter charge-pump PLL is built in 90-nm CMOS for 1-10 Gb/s SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integrating path and novel resistorless proportional path that can be independently controlled an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cee974ca437790452bdb0cc98a80cbff
https://doi.org/10.1109/cicc.2005.1568728
https://doi.org/10.1109/cicc.2005.1568728
Publikováno v:
International Technical Digest on Electron Devices Meeting.
A novel disposable TiN LDD/salicide spacer process has been developed for a 0.5- mu m CMOS technology. Both LDD (lightly doped drain) and salicide definition are obtained using a single disposable TiN spacer. This process results in CMOS devices with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c73811d8d96429c22239626564e5f2b
https://doi.org/10.1109/iedm.1989.74170
https://doi.org/10.1109/iedm.1989.74170
Publikováno v:
Technical Digest., International Electron Devices Meeting.
Experiments and simulations have been performed which indicate three important effects of implantation damage on arsenic-phosphorus codiffusion. First, the profiles are primarily determined by the damage-induced injection of defects. Second, damage e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a7a78424345614243b9f02cad565ac71
https://doi.org/10.1109/iedm.1988.32895
https://doi.org/10.1109/iedm.1988.32895
Publikováno v:
Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting.
A techinque is presented for forming an ultrashallow link base in a double polysilicon bipolar transistor. This method is easily integrated into an advanced BiCMOS process, making use of a disposable polysilicon spacer technology for MOSFET lightly d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b967179525c01bf180e7b45defe6084
https://doi.org/10.1109/bipol.1992.274075
https://doi.org/10.1109/bipol.1992.274075
Autor:
Y.-C. Ku, S.D. Hayden, K. Mocala, F J W Miller, M. Blackwell, C.K. Subramanian, W. Waldo, S. Ajuria, Matthew A. Thompson, J.R. Pfiester, B.M. James, B. Martino, H.-J. Lin
Publikováno v:
Proceedings of 1994 IEEE International Electron Devices Meeting.
A 0.25 /spl mu/m CMOS technology designed for a new symmetric Vss Cross-Under (XUnder) bitcell has been developed for a 64 Mb SRAM. The new symmetric bitcell is based on a simple geometry of orthogonal active and gate poly features which minimizes th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b898697baf8bd30c2b5613524a09918d
https://doi.org/10.1109/iedm.1994.383333
https://doi.org/10.1109/iedm.1994.383333
Publikováno v:
IEEE Electron Device Letters. 12:584-586
P-channel MOS thin-film transistors (TFTs) have been fabricated in low-pressure chemical vapor deposition (LPCVD) polycrystalline silicon-germanium (poly-SiGe) films using either a low-temperature ( >
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d17f7f2a0ca93986095e26503f57d77
https://doi.org/10.1109/55.119205
https://doi.org/10.1109/55.119205
Autor:
J.R. Pfiester, F.K. Baker
Publikováno v:
IEEE Transactions on Electron Devices. 35:2119-2124
Asymmetries in MOSFET high-field effects, such as impact ionization and bipolar snapback, are used to examine the influence of tilted source-drain implants on device reliability. Several process variables, including source-drain implant conditions an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6956273a4f61f53f173f51c991508fed
https://doi.org/10.1109/16.8785
https://doi.org/10.1109/16.8785
Autor:
J.R. Pfiester
Publikováno v:
IEEE Electron Device Letters. 9:189-192
A technology for fabricating lightly doped drain (LDD) MOSFET devices based on disposable sidewall spacers is presented. Using a thin polysilicon buffer layer between the low-temperature oxide (LTO) sidewall spacers and the oxidized polysilicon gate,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66fc3cccdbcbe03d12c133203ca3bb2c
https://doi.org/10.1109/55.685
https://doi.org/10.1109/55.685
Publikováno v:
IEEE Electron Device Letters. 9:343-346
Germanium doping in silicon tends to suppress any enhancement in dopant diffusion due to excess point defects. By performing a dual implantation of germanium and the normal source-drain dopant, lateral diffusion of the source-drain profile can be con
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f158bed425556b1e0a3f9a9e40939532
https://doi.org/10.1109/55.738
https://doi.org/10.1109/55.738