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Akademický článek
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Akademický článek
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Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:553-563
One of the challenges of designing for coarse-grain reconfigurable arrays is the need for mature tools. This is especially important because of the heterogeneity of the larger, more predefined (and hence more specialized) array elements. This work de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f52bbf1fe09871c1f8dac2398afcbfdf
https://doi.org/10.1109/tvlsi.2005.844286
https://doi.org/10.1109/tvlsi.2005.844286
Autor:
J.P. Knight, R.R. Ortiz
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10:327-340
Dynamic logic is an alternative way of making logic circuit cells and numerous techniques have been developed to take advantage of its unique characteristics. Particularly, techniques such as the true-single-phase-clock (TSPC) have been used very suc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4fd4efa65be6562777dc16c43b6d3153
https://doi.org/10.1109/tvlsi.2002.1043336
https://doi.org/10.1109/tvlsi.2002.1043336
Autor:
J.P. Knight, E. Torbey
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 9:599-607
Selecting a clock period is an essential step in implementing hardware from behavioral descriptions. Current methods either estimate the clock prior to scheduling or involve exhaustive runs of the high-level synthesis tools to obtain a globally optim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e9d0be53fb5c3a2c9524a062d8c2e1f
https://doi.org/10.1109/92.953494
https://doi.org/10.1109/92.953494
Autor:
R. San Martin, J.P. Knight
Publikováno v:
IEEE Design & Test of Computers. 13:58-70
Attacking power consumption at the behavioral level exploits an application's inherent parallelism to maintain performance while compensating for slower, less power-hungry operators. The authors' method and tool optimize and evaluate the effects of p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2947a7735e3f897bb8ad4625948ef102
https://doi.org/10.1109/54.500201
https://doi.org/10.1109/54.500201
Autor:
Raul San Martin, J.P. Knight
Publikováno v:
Computers & Operations Research. 20:845-856
The acceptance of high-level synthesis tools and methodologies by the design engineers depends on their efficiency in producing circuits with small silicon areas and high operating speeds. This paper shows how this efficiency can be achieved through
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a2a1ac3b58f294e6563a9e473965766
https://doi.org/10.1016/0305-0548(93)90106-s
https://doi.org/10.1016/0305-0548(93)90106-s
Autor:
J.P. Knight, G. Allan
Publikováno v:
ISCAS
A new filtering method significantly reduces DLL/PLL area, power and integration complexity. A compact delay-line structure generates a thermometer-coded control string, in which most bits are held at 0 or 1, but a few cells at the code's transition
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0956f4958b4a80bdfc805ba20ac9078f
https://doi.org/10.1109/iscas.2006.1693122
https://doi.org/10.1109/iscas.2006.1693122
Autor:
J.P. Knight, G. Allan
Publikováno v:
ISCAS
A compact low-power PLL is implemented in 0.18 /spl mu/m CMOS for clock management and distribution. Like digital PLLs, it is composed of standard-cells, can be mixed with regular logic, and is digitally placed & routed, but it does not suffer from q
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f5ccf57582f7b94c149a280402fe100
https://doi.org/10.1109/iscas.2006.1693121
https://doi.org/10.1109/iscas.2006.1693121
Autor:
J.P. Knight, G. Allan
Publikováno v:
ISCAS (2)
A novel digital circuit is presented which, given one asynchronous training pulse, performs reliable clock and data recovery (CDR) on a bit-stream at rates up to 1.3 Ghz/Gbps. The circuit requires no analog components and is suitable for implementati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9bd07ef7d876eb510bac2858a41c2362
https://doi.org/10.1109/iscas.2004.1329333
https://doi.org/10.1109/iscas.2004.1329333