Zobrazeno 1 - 10
of 50
pro vyhledávání: '"J.N. Albers"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:205-211
This paper introduces a modification of the feedback emitter-coupled logic (FECL) gate that makes it suitable for Gb/s applications. The circuit can be used as a single-ended-to-differential signal converter without the need for an external reference
Publikováno v:
Solid-State Electronics. 41:1105-1110
A significant reduction of parasitic resistances and capacitances of the double mesa SiGe Heterojunction Bipolar Transistors (SiGe-HBT) was achieved by using self-aligned processing steps, such as planarization of transistor contacts, outside-spacer-
Publikováno v:
Solid-State Electronics. 39:471-480
Broad-band and wireless communication seem to be a technology battleground, with new high performance demands to the applied active and passive devices, and the optimization of circuit design. Up to now, there are several technologies for low power a
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:54-60
A 1:4-demultiplexer IC meeting the essential requirements for lightwave communication systems has been designed based on a 21 GHz f/sub T/ 0.4 /spl mu/m Si bipolar process. The circuit provides features such as bit-rotation control, clock enable cont
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:129-132
The 4:1-multiplexer reported here is based on a 21 GHz f/sub T/ 0.4 /spl mu/m silicon bipolar technology and operates up to 12 Gb/s. For facilitating system applications, the input signals are aligned in phase and retiming of the output signal is pro
Publikováno v:
Journal of Lightwave Technology. 12:320-324
This paper presents a 20-Gb/s 1:4-demultiplexer for future fiber-optic transmission systems. It uses an 0.4-/spl mu/m emitter double polysilicon 21-GHz f/sub T/ Si bipolar foundry process. This is the highest data rate of a 1:4-DEMUX reported so far
Autor:
H.-U. Schreiber, J.N. Albers
Publikováno v:
IEEE Journal on Selected Areas in Communications. 9:652-655
A multiplexer operating at up to 12 Gb/s has been demonstrated using a simple, but optimized, silicon bipolar technology with 2 mu m lithography. Using this simple but optimized technology, a 12 Gb/s multiplexer was implemented. Circuit simulations p
Publikováno v:
IEEE Photonics Technology Letters. 9:82-84
A DC-coupled 4-channel synchronous optical receiver with 8-Gb/s aggregate throughput has been designed using a monolithic silicon bipolar IC and an InGaAs p-i-n photodiode array. Each channel employs a positive feedback structure to dynamically gener
Publikováno v:
IEEE Photonics Technology Letters. 8:685-687
A monolithic broad-band dc-coupled Silicon bipolar optical transducer has been designed to receive and retime uncoded data at rates up to 2.5 Gb/s. The transducer employs a modified feedback emitter coupled logic (FECL) loop to dynamically set refere
Publikováno v:
Electronics Letters. 30:1214-1216
A 1:16-demultiplexer based on silicon bipolar 1:4-demultiplexer ICs, which include all requirements for system applications, has been designed and tested. The authors report the design of the 1:4-demultiplexer, which operates up to 14 Gbit/s, and exp