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Autor:
John George Petrovick, Jack DiLullo, Carl J. Anderson, J. Keaty, Joachim Gerhard Clabes, Shao-Fu S. Chu, P. E. Dudley, James D. Warnock, J. Wagoner, G. Nussbaum, S. Weitzel, B. A. Zoric, R. Weiss, G. Plum, Steve Runyon, Byron L. Krauter, Bradley McCredie, Pong-Fei Lu, S. Schmidt, Michael R. Scheuermann, Phillip J. Restle, Craig R. Carter, J. LeBlanc, J.M. Tendier, P. Harvey
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu