Estimating Failure Probabilities

Autor: Roland Pulch, J.J. Dohmen, E. Jan W. ter Maten, Theo G. J. Beelen, Aarnout Wieers, Frederik Deleu, Alessandro Di Bucchianico, Rick Janssen, Ulrich Römer, Herbert De Gersem, Renaud Gillon, Bratislav Tasić

Publikováno v: Mathematics in Industry ISBN: 9783030307257

System failure describes an undesired configuration of an engineering device, possibly leading to the destruction of material or a significant loss of performance and a consequent loss of yield. For systems subject to uncertainties, failure probabili

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::30f9aa8119362d80c806af10bfc7f14c
https://doi.org/10.1007/978-3-030-30726-4_16

Fitting Generalized Gaussian Distributions for Process Capability Index

Autor: Bratislav Tasić, J.J. Dohmen, Theo G. J. Beelen, E. Jan W. ter Maten

Publikováno v: Scientific Computing in Electrical Engineering ISBN: 9783319755373

The design process of integrated circuits (IC) aims at a high yield as well as a good IC-performance. The distribution of measured output variables will not be standard Gaussian anymore. In fact, the corresponding probability density function has a m

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7f2d23cc9dd99aa1e2edb8172b2bf754
https://doi.org/10.1007/978-3-319-75538-0_16

Fast time-domain simulation for reliable fault detection

Autor: Roland Pulch, E. Jan W. ter Maten, J.J. Dohmen, Rick Janssen, Bratislav Tasić, Theo G. J. Beelen

Publikováno v: Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, 301-306
STARTPAGE=301;ENDPAGE=306;TITLE=Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
DATE

Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, “golden”, design of an electronic circuit. By fault simulation we simulate all situations: a huge number of new connections and each w

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0556c0577f3abad03aafe1c56dcd7c76
https://research.tue.nl/nl/publications/11a6115d-ca1f-4bfc-b910-793d03b5d32d

Defect Oriented Testing for Analog/Mixed-Signal Designs

Autor: M. van Beurden, Hamidreza Hashempour, J.J. Dohmen, Bratislav Tasić, B. Kruseman, C. Hora, Yizi Xing

Publikováno v: IEEE Design & Test of Computers. 29:72-80

In this contribution, the authors describe an application of Defect Oriented Testing (DOT) to commercial mixed-signal designs. A major challenge of DOT application to these designs is the enormous simulation time typically required. The authors addre

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e4e7fac94199ba86492a8b5e0377270f
https://doi.org/10.1109/mdt.2012.2210852

Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example

Autor: Bratislav Tasić, B. Kruseman, Maikel van Beurden, Hamidreza Hashempour, C. Hora, J.J. Dohmen, Yizi Xing

Publikováno v: DATE

We present an application of Defect Oriented Testing (DOT1) to an industrial mixed signal device to reduce test time and maintain quality. The device is an automotive IC product with stringent quality requirements and a mature test program that is al

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::73ce4218237bee34b58e494805d311d0
https://doi.org/10.1109/date.2011.5763065