Zobrazeno 1 - 7
of 7
pro vyhledávání: '"J.D. Pickholtz"'
Autor:
M.J. Smith, S. Felix, Shane L. Bell, J.D. Pickholtz, R.W. Badeau, Swati Mehta, M.K. Gowan, D.B. Jackson, Matthew H. Reilly, R. Gammack, Paul E. Gronowski, S.V. Morton, William J. Bowhill, L.L. Biro, D.W. Bailey, V. Germini, R.P. Preston, D.E. Dever
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
A 250M transistor microprocessor implements the Alpha instruction set and features 8-wide superscalar issue and simultaneous multithreading in a 0.125/spl mu/m SOI process. Performance is estimated at over three times that of the previous design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e2a802a8f4a58c87d094dcd0d3f4bc4
https://doi.org/10.1109/isscc.2002.992247
https://doi.org/10.1109/isscc.2002.992247
Autor:
Elizabeth M. Cooper, William J. Bowhill, B.J. Benschneider, V.K. Maheshwari, M.N. Gavrielov, J.D. Pickholtz, Paul E. Gronowski, Sridhar Samudrala, V. Peng
Publikováno v:
IEEE International Solid-State Circuits Conference.
A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e02992ff7681e16ec7ad38bbda92832
https://doi.org/10.1109/isscc.1989.48229
https://doi.org/10.1109/isscc.1989.48229
Autor:
V. Peng, Sridhar Samudrala, Elizabeth M. Cooper, W.V. Herrick, A Fisher, D.E. Sanders, Randy L. Allmon, W.H. Durdan, Paul E. Gronowski, D. Kravitz, P.J. Starvaski, L. Madden, R.C. Marcello, V.K. Maheshwari, G.G. Mills, J.F. Brown, William J. Bowhill, W.R. Wheeler, M. Mittal, W.J. Grundmann, M.N. Gavrielov, J.D. Pickholtz, B.J. Benschneider, R.L. Stamm
Publikováno v:
IEEE International Solid-State Circuits Conference.
A four-chip custom VLSI implementation of a 32-b computer comprised of a CPU, a secondary cache controller, a floating-point accelerator, and a clock generator is described. It operates at a cycle time of 28 ns and is compatible with an existing comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29c00422818686241ddc04191e4d092c
https://doi.org/10.1109/isscc.1989.48187
https://doi.org/10.1109/isscc.1989.48187
Autor:
L. Hudepohl, R. Allmon, S. Samudrala, D.E. Dever, J. Farrell, R.C. Marcello, D.E. Sanders, J. Lundberg, N. Fitzgerald, M. Richesson, J. Grodstein, L. Chao, B.J. Benschneider, J.D. Pickholtz, M. Callander, Soha Hassoun, D. Kravitz, S. Marino, R.P. Preston
Publikováno v:
1990 37th IEEE International Conference on Solid-State Circuits.
The system, process, and design implications of converting a microprocessor chip set originally implemented in a 5-V, 1.5- mu m (drawn) CMOS process to one implemented in a 3.3-V, 1.0- mu m (drawn) CMOS process are described. The chip set is 75% fast
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fa689077638e7c2fea5866d175603aa
https://doi.org/10.1109/isscc.1990.110123
https://doi.org/10.1109/isscc.1990.110123
Autor:
V. Peng, W.J. Bowhill, V.K. Maheshwari, S. Samudrala, P.E. Gronowski, E.M. Copper, B.J. Benschneider, M.N. Gavrielov, J.D. Pickholtz
Publikováno v:
IEEE Journal of Solid-State Circuits. 24:1317-1323
A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except do
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae6b8abdcaf9a0bc6464df57fb918bc0
https://doi.org/10.1109/jssc.1989.572606
https://doi.org/10.1109/jssc.1989.572606
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Akademický článek
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