Zobrazeno 1 - 10
of 83
pro vyhledávání: '"J.B. Kuang"'
Autor:
Jeremy D. Schaub, Kevin J. Nowka, Sani R. Nassif, J.B. Kuang, D. Wendel, T. Frohnel, Fadi H. Gebara, S. Saroop
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 58:2010-2016
Dual read port 6-transistor (6T) SRAMs play a critical role in high-performance cache designs thanks to doubling of access bandwidth, but stability and sensing challenges typically limit the low-voltage operation. We report a high-performance dual re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a42e97366930d914cf6d9a75cd6bded
https://doi.org/10.1109/tcsi.2011.2162459
https://doi.org/10.1109/tcsi.2011.2162459
Publikováno v:
IEEE Transactions on Electron Devices. 56:3033-3040
This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area pe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f32b7d9d29c928d9b67aa7172374e5d6
https://doi.org/10.1109/ted.2009.2030657
https://doi.org/10.1109/ted.2009.2030657
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16:1657-1665
Independent gate control in double-gate (DG) devices enhances circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we describe circuit techniques which take advantage of the independent biasing propert
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::086522ee1bedc5ef30cdc01016a97f3e
https://doi.org/10.1109/tvlsi.2008.2001564
https://doi.org/10.1109/tvlsi.2008.2001564
Autor:
Ching-Te Chuang, J.B. Kuang
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 51:349-353
This paper presents a new circuit technique to alleviate the uncontrollable floating-body-induced hysteretic component present in the transfer characteristics of voltage-mode CMOS Schmitt trigger circuits in a partially depleted silicon-on-insulator
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3117b8900e880cd1e8b0f1ddd31f480c
https://doi.org/10.1109/tcsii.2004.831428
https://doi.org/10.1109/tcsii.2004.831428
Publikováno v:
ESSCIRC
A compact SRAM ring oscillator circuit for local, in-situ, probing of device performance is described. Applied to three-dimensional integrated circuit technology (3DI), the circuit is used to determine if there is any effect on SRAM performance when
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1b1cc510b2bf0e8112315bb0fb6f105
https://doi.org/10.1109/esscirc.2013.6649162
https://doi.org/10.1109/esscirc.2013.6649162
Autor:
Fadi H. Gebara, D. Wendel, J.B. Kuang, Jeremy D. Schaub, S. Saroop, Tuyen V. Nguyen, B. Lloyd, C.M. Durham, J. Pille, Kevin J. Nowka, A. Muller, Sani R. Nassif, B. Robbins, T. Frohnel, Rolf Sautter
Publikováno v:
CICC
Dual read port SRAMs play a critical role in high performance cache designs, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0aeb174b09931e07d1230503d185e22a
https://doi.org/10.1109/cicc.2010.5617630
https://doi.org/10.1109/cicc.2010.5617630
Publikováno v:
Solid-State Electronics. 35:1203-1208
High-performance p-n-p transistors have been fabricated utilizing the conventional self-aligned ion-implanted double-polysilicon approach. In the present profile and process design, heat cycle compatibility with the n-p-n transistor process was prese
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::234dae3b8dc53308cae1ce933763e004
https://doi.org/10.1016/0038-1101(92)90149-7
https://doi.org/10.1016/0038-1101(92)90149-7
Publikováno v:
2008 IEEE International SOI Conference.
The proposed selective-back gate bias technique using dual BOX improves SRAM stability, reduce leakage power, and enhances sub-array access speed while preserving overall area efficiency. TCAD simulations show that nominal Read SNM is improved by 37%
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11a70000c168408c0103f113240349ee
https://doi.org/10.1109/soi.2008.4656283
https://doi.org/10.1109/soi.2008.4656283
Autor:
Jeremy D. Schaub, Ivan Vo, William Robert Reohr, Kevin J. Nowka, Donald W. Plass, Erik A. Nelson, John E. Barth, Tuyen V. Nguyen, Gary D. Carpenter, Abraham Mathews, T. Kirihata, Fadi H. Gebara, J.B. Kuang
Publikováno v:
ESSCIRC
We present an on-chip word line (WL) dual supply system for server class embedded DRAM (eDRAM) applications. The design consists of switched capacitor charge pumps, voltage regulators, reference and clock circuits. Charge pump engines feature efficie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c7cd7688b85297687daf541d6593b56
https://doi.org/10.1109/esscirc.2008.4681793
https://doi.org/10.1109/esscirc.2008.4681793
Publikováno v:
IEEE Transactions on Electron Devices. 37:1948-1958
A self-aligned nitrogen implantation process (SNIP) utilizing low-energy and high-dose molecular nitrogen ions has been developed to minimize the field oxide thinning effect in submicrometer local oxidation of silicon (LOCOS) isolation. Molecular nit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::43666567c275108ea582e8d2dbebf6dc
https://doi.org/10.1109/16.57155
https://doi.org/10.1109/16.57155