Zobrazeno 1 - 10
of 20
pro vyhledávání: '"J.B. Burr"'
Publikováno v:
2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..
Edge-defined nano-meter scale lines patterned in silicon using 1/spl mu/m optical lithography with standard materials and processing equipment are compatible with low thermal budget 3-D IC processes. A chemical vapor deposition (CVD) process is used
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e66d1febd6f6978e1564247f99b3c63
https://doi.org/10.1109/nano.2003.1230956
https://doi.org/10.1109/nano.2003.1230956
Publikováno v:
1988., IEEE International Symposium on Circuits and Systems.
A novel architecture to implement distributed arithmetic in VLSI is presented. This architecture comprises a serial-in random-out multiport memory and a multi-input adder. The design of a 1.25- mu m CMOS convolution processor chip based on the archit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c635ff11de11a6a7d5eeff4d1af8eb8b
https://doi.org/10.1109/iscas.1988.15217
https://doi.org/10.1109/iscas.1988.15217
Autor:
Michael Murray, Kan Boonyanit, J.B. Burr, Ming-Tak Leung, Gregory J. Wolff, A. M. Peterson, David G. Stork
Publikováno v:
ASAP
Describes a special purpose, very high speed, digital deterministic Boltzmann neural network VLSI chip. Each chip has 32 physical neural processors, which can be apportioned into an arbitrary topology (input, multiple hidden and output layers) of up
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8cb3f1f0d221e3f567f31c1c94b10644
https://doi.org/10.1109/asap.1992.218571
https://doi.org/10.1109/asap.1992.218571
Publikováno v:
IPPS
Permutation is a common problem in both computation and communication. The authors add the buses to the mesh-connected multiprocessors and introduce the tokens to control the buses. They propose to use the mesh with segmented reconfigurable bus to in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::daf40be2cf185d713c15cf1bedb983cc
https://doi.org/10.1109/ipps.1993.262896
https://doi.org/10.1109/ipps.1993.262896
Publikováno v:
1996 Symposium on VLSI Circuits. Digest of Technical Papers.
For remote-sensing and portable video encoding applications, reducing power consumption is important due to the limited power budget. In systems such as MPEG, motion estimation (ME) accounts for most of the compression and computation. In ME processi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7a04e899133d7ee6e4a603a3a29faf01
https://doi.org/10.1109/vlsic.1996.507755
https://doi.org/10.1109/vlsic.1996.507755
Publikováno v:
1996 Symposium on VLSI Circuits. Digest of Technical Papers.
We designed and implemented a wormhole data router chip for 2-D meshes with bi-directional channels and token-exchange arbitration. In our design, the token-exchange delay is fully hidden and no latency penalty occurs when there is no traffic content
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a7cc8d5a54d2f1c7928fe324b2ee32ee
https://doi.org/10.1109/vlsic.1996.507745
https://doi.org/10.1109/vlsic.1996.507745
Publikováno v:
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
A CMOS test chip that includes a 1k-transistor self-testing encoder/decoder is verifiably error-free at supply voltages down to 20O mV, achieving 1/625 the power-delay product of standard 5 V CMOS. The maximum error-free operating frequency of this c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9583c60de3946cb5dbf14d21ecbcaa32
https://doi.org/10.1109/isscc.1994.344717
https://doi.org/10.1109/isscc.1994.344717
Autor:
J.B. Burr, A.M. Peterson
Publikováno v:
ICCD
Multichip modules permit highly efficient implementation of tiled architectures. If the tiles are implemented in submicron CMOS, extremely highly computation rates can be achieved, but power dissipation becomes the principal factor limiting achievabl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ffcbf2be24f5c177e0138883b6c4452
https://doi.org/10.1109/iccd.1991.139981
https://doi.org/10.1109/iccd.1991.139981
Autor:
J.B. Burr
Publikováno v:
1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.
This paper reports 7-stage 1.5 /spl mu/m zeroVt CMOS ring oscillators operating at 170 MHz/V down to V/sub dd/=70 mV at room temperature, and 360 MHz/V down to V/sub dd/=27 mV at 77 K.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::278981b8397761d08ec1d13d1bc8c470
https://doi.org/10.1109/lpe.1995.482473
https://doi.org/10.1109/lpe.1995.482473
Publikováno v:
ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).
An 80,000 transistor, low swing, 32/spl times/32-bit multiplier was fabricated in a standard 0.35 /spl mu/m, V/sub th/=0.5 V CMOS process and in a 0.35 /spl mu/m, back-bias tunable, near-zero V/sub th/ process. While standard CMOS at V/sub dd/=3.3 V
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cfd9f762b367f9d3254432c45865a31a
https://doi.org/10.1109/lpe.2000.155297
https://doi.org/10.1109/lpe.2000.155297