Zobrazeno 1 - 10
of 237
pro vyhledávání: '"J.-P. Colinge"'
Autor:
Benoit Sklenard, Joris Lacord, D. Lattard, R. Nait Youcef, Xavier Garros, A. Tataridou, Francois Andrieu, Claire Fenouillet-Beranger, F. Balestra, Sylvain Barraud, Perrine Batude, G. Audoit, Mikael Casse, D. Bosch, J. Lugo, Christoforos G. Theodorou, Laurent Brunet, J.-P. Colinge, J. Cluzel, F. Allain, C. Vizioz, J.M. Hartmann
Publikováno v:
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Aug 2020, Hsinchu, Taiwan. pp.126-127, ⟨10.1109/VLSI-TSA48913.2020.9203690⟩
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Aug 2020, Hsinchu, Taiwan. pp.126-127, ⟨10.1109/VLSI-TSA48913.2020.9203690⟩
We fabricated junction less and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junction less transistors for analog applications: $A_{VT}=1.4mV \cdot \mu$ m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::22aa19246805ca5305905064aa067feb
https://hal.science/hal-02969748/file/vlsi_tsa_BOSCH_HAL.pdf
https://hal.science/hal-02969748/file/vlsi_tsa_BOSCH_HAL.pdf
Autor:
F. Balestra, C. Perrot, Joris Lacord, Didier Lattard, Perrine Batude, Benoit Sklenard, V. Benevent, P. Acosta Alba, Sebastien Kerdiles, D. Bosch, Claire Fenouillet-Beranger, J. Lassarre, J. Richy, Francois Andrieu, J.-P. Colinge, Laurent Brunet
Publikováno v:
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-sili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c9ce1f179d7606adeb1a27fcb299c07c
Autor:
Perrine Batude, Gerard Ghibaudo, Gilles Sicard, O. Rozeau, C. Fenouillet-Beranger, Christoforos G. Theodorou, Francois Andrieu, Sebastien Kerdiles, P. Sideris, Jose Lugo-Alvarez, Laurent Brunet, P. Acosta-Alba, J.-P. Colinge
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM)
2019 IEEE International Electron Devices Meeting (IEDM), Dec 2019, San Francisco, United States. pp.3.4.1-3.4.4, ⟨10.1109/IEDM19573.2019.8993493⟩
2019 IEEE International Electron Devices Meeting (IEDM), Dec 2019, San Francisco, United States. pp.3.4.1-3.4.4, ⟨10.1109/IEDM19573.2019.8993493⟩
International audience; For the first time, an in-depth analysis of the intertier dynamic coupling and RF crosstalk of digital circuits in 3D sequential integration enables to conclude on the need of a Ground Plane (GP) for various applications. Expe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ee68b1ce50791417b94da9ca932a2953
https://hal.science/hal-02969757
https://hal.science/hal-02969757
Autor:
C. Le Royer, C. Diaz Llorente, Jing Wan, Gerard Ghibaudo, Sebastien Martinie, J.-P. Colinge, Maud Vinet, Sorin Cristoloveanu
Publikováno v:
Solid-State Electronics
Solid-State Electronics, 2019, 159, pp.26-37. ⟨10.1016/j.sse.2019.03.046⟩
Solid-State Electronics, Elsevier, 2019, 159, pp.26-37. ⟨10.1016/j.sse.2019.03.046⟩
Solid-State Electronics, 2019, 159, pp.26-37. ⟨10.1016/j.sse.2019.03.046⟩
Solid-State Electronics, Elsevier, 2019, 159, pp.26-37. ⟨10.1016/j.sse.2019.03.046⟩
We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low ION and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a893643504e603f01228043a07bbc449
https://hal.science/hal-02321885
https://hal.science/hal-02321885
Autor:
Francois Andrieu, L. Ciampolini, G. Cibrario, F. Balestra, Joris Lacord, Xavier Garros, Perrine Batude, Laurent Brunet, A. Makosiej, D. Lattard, Bastien Giraud, Maud Vinet, Claire Fenouillet-Beranger, J.-P. Colinge, Olivier Weber, J. Cluzel, D. Bosch
Publikováno v:
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2019, Grenoble, France. pp.1-4, ⟨10.1109/EUROSOI-ULIS45800.2019.9041890⟩
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2019, Grenoble, France. pp.1-4, ⟨10.1109/EUROSOI-ULIS45800.2019.9041890⟩
International audience; We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5a29cff3968e6920ebe18ab7cb26addf
https://hal.archives-ouvertes.fr/hal-02998370
https://hal.archives-ouvertes.fr/hal-02998370
Autor:
F. Balestra, A. Makosiej, Joris Lacord, Maud Vinet, Laurent Brunet, E. Esmanhotto, Francois Andrieu, Marco Rios, J. Cluzel, G. Cibrario, Perrine Batude, Olivier Weber, R. Berthelon, D. Lattard, D. Bosch, L. Ciampolini, Claire Fenouillet-Beranger, J.-P. Colinge, Bastien Giraud, S. Lang, Xavier Garros
Publikováno v:
2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).
For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6339fddbd9f229a6f65ff13fd410189d
https://doi.org/10.1109/vlsi-tsa.2019.8804649
https://doi.org/10.1109/vlsi-tsa.2019.8804649
Publikováno v:
Journal of Telecommunications and Information Technology, Iss 1 (2001)
The paper reviews the problems related to BOX high-temperature instability in SOI structures and MOSFETs. The methods of bias-temperature research applied to SOI structures and SOI MOSFETs are analysed and the results of combined electrical studies o
Externí odkaz:
https://doaj.org/article/11c7a9f538fe4c0fad97d0637c2c79b0
Autor:
Francois Andrieu, Joris Lacord, R. Berthelon, Laurent Brunet, A. Makosiej, Olivier Weber, C. Fenouillet-Beranger, X. Garros, G. Cibrario, D. Lattard, J.-P. Colinge, J. Cluzel, Lorenzo Ciampolini, D. Bosch, Perrine Batude, F. Balestra, Bastien Giraud
Publikováno v:
Solid-State Electronics. 168:107720
For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::693fb96b0d9182cfb46ea634695f9b9a
https://doi.org/10.1016/j.sse.2019.107720
https://doi.org/10.1016/j.sse.2019.107720
Autor:
C. Diaz-Llorente, Maud Vinet, Sorin Cristoloveanu, Gerard Ghibaudo, Christoforos G. Theodorou, J.-P. Colinge, C. Le Royer
Publikováno v:
2018 S3S Proceedings
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2018, San Francisco, United States. pp.5.4, ⟨10.1109/S3S.2018.8640190⟩
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2018, San Francisco, United States. pp.5.4, ⟨10.1109/S3S.2018.8640190⟩
session: 3D technology II; International audience; Tunnel FETs fabricated using the low-temperature Cool Cube TM process are compared with devices made with standard high-temperature (HT) technology. Charge pumping (CP) and low-frequency noise (LFN)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c8eae9c506bfc8d061951f22f24ac99e
https://doi.org/10.1109/s3s.2018.8640190
https://doi.org/10.1109/s3s.2018.8640190
Autor:
J.-P. Colinge, Gerard Ghibaudo, Perrine Batude, C-M. V. Lu, F. Allain, C. Le Royer, C. Fenouillet-Beranger, M. Vinet, Sorin Cristoloveanu, C. Diaz Llorente, Sebastien Martinie
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2018, 144, pp.78-85. ⟨10.1016/j.sse.2018.03.006⟩
Solid-State Electronics, 2018, 144, pp.78-85. ⟨10.1016/j.sse.2018.03.006⟩
Solid-State Electronics, Elsevier, 2018, 144, pp.78-85. ⟨10.1016/j.sse.2018.03.006⟩
Solid-State Electronics, 2018, 144, pp.78-85. ⟨10.1016/j.sse.2018.03.006⟩
International audience; This paper reports the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) made using a Low-Temperature (LT) process designed for 3D sequential integration. These proof-of-concept TFETs feature juncti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::132343776d14328efad9eaef1849964b
https://hal.archives-ouvertes.fr/hal-01948037
https://hal.archives-ouvertes.fr/hal-01948037