Zobrazeno 1 - 10
of 21
pro vyhledávání: '"J.-M. Pedini"'
Publikováno v:
Scientific Reports, Vol 12, Iss 1, Pp 1-11 (2022)
Abstract In this work, we present an on-chip 2D and 3D photonics integration solution compatible with Front End of Line integration (FEOL) using deposited polycrystalline silicon (poly:Si) for optical interconnects applications. Deposited silicon int
Externí odkaz:
https://doaj.org/article/84f9b2dbf5cb461da34f0dde10d6a6e2
Autor:
L. Lachal, C. Plantier, F. Torregrosa, C. Aubert, J. M. Pedini, G. Borvon, M. Coig, F. Milesi, F. Mazen
Publikováno v:
MRS Advances. 7:1390-1394
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc061e3c5633a5613ec1496d49cde248
https://doi.org/10.1557/s43580-022-00468-z
https://doi.org/10.1557/s43580-022-00468-z
Autor:
F. Aussenac, P. Acosta-Alba, V. Beugin, V. Mazzocchi, Xavier Garros, Mikael Casse, Sebastien Kerdiles, C. Vizioz, C. Guerin, N. Rambal, F. Ponthenier, J. Micout, Perrine Batude, Maud Vinet, Bernard Previtali, Francois Andrieu, Claire Fenouillet-Beranger, S. Chevalliez, J-M. Pedini, Laurent Brunet
Publikováno v:
2019 Electron Devices Technology and Manufacturing Conference (EDTM).
This paper highlights the last technological breakthroughs achieved in the development of low temperature process modules at 500°C for 3D sequential integration. The two remaining process steps (low temperature gate stack and selective silicon raise
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2087db0598ab33110cf86534df124584
https://doi.org/10.1109/edtm.2019.8731192
https://doi.org/10.1109/edtm.2019.8731192
Autor:
D. Barge, Thibaud Denneulin, C. Le Royer, David Cooper, Jean-Paul Barnes, P. Nguyen, O. Bonnin, J. M. Pedini, Olivier Gourhant, E. Baylac, Walter Schwarzenbach, Yves Campidelli, F. Glowacki, Y. Morand, Jean-Michel Hartmann, Denis Rouchon
Publikováno v:
Solid-State Electronics. 97:82-87
300 mm ultrathin Silicon-On-Insulator (SOI) wafers with SiGe/Si stacks on top were used as pre-structures for the fabrication of 5 nm thick SiGe-On-Insulator (SGOI) substrates obtained by the Ge enrichment technique. Those substrates will be used as
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19b1ec5e7275fcbef97299a0ef893e41
https://doi.org/10.1016/j.sse.2014.04.026
https://doi.org/10.1016/j.sse.2014.04.026
Autor:
C. Plantier, Frederic Boeuf, Maud Vinet, J.M. Hartmann, Michel Haond, Claude Tabone, Anthony Payet, Yves Morand, A. Bonnevialle, J. M. Pedini, Denis Rouchon, Shay Reboh, N. Rambal, C. Le Royer, Alain Claverie
Publikováno v:
physica status solidi (c)
physica status solidi (c), Wiley, 2016, 13 (10-12), pp.740-745. ⟨10.1002/pssc.201600028⟩
physica status solidi (c), 2016, 13 (10-12), pp.740-745. ⟨10.1002/pssc.201600028⟩
physica status solidi (c), Wiley, 2016, 13 (10-12), pp.740-745. ⟨10.1002/pssc.201600028⟩
physica status solidi (c), 2016, 13 (10-12), pp.740-745. ⟨10.1002/pssc.201600028⟩
cited By 1; International audience; Strain boosters are an effective way to improve performances in advanced CMOS FDSOI devices. Hole mobility is higher in pFETs with compressive channels. Meanwhile, electron mobility is higher for nFETs with tensile
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1e1555082c054d6594e7b57487b43538
https://hal.archives-ouvertes.fr/hal-01719490
https://hal.archives-ouvertes.fr/hal-01719490
Autor:
C. Plantier, Pascal Besson, C. Le Royer, A. Bonnevialle, Michel Haond, Remy Berthelon, M. Vinet, Olivier Weber, M. Casse, S. Reboh, J-M. Pedini, Yves Morand, Alain Claverie, J.M. Hartmann, B. Mathieu, D. Rouchon, Francois Andrieu, Frederic Boeuf, D. Marseilhan, Sebastien Kerdiles, N. Rambal
Publikováno v:
VLSI Technology, 2016 IEEE Symposium on
VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573406⟩
2016 IEEE Symposium on VLSI Technology
VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573406⟩
2016 IEEE Symposium on VLSI Technology
cited By 1; International audience; We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. 'STRASS' and 'BOX creep' techniques (for tensily and compressively stressed channels, respectively) are for the fir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f40591e840f3628feb44812ad9fa4d18
https://hal.science/hal-01719489
https://hal.science/hal-01719489
Akademický článek
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Autor:
A. Roule, Nicolas Bernier, Maud Vinet, C. Plantier, J. M. Pedini, C. Le Royer, L. Grenouillet, Y. Morand, A. Bonnevialle, D. Marseilhan, Claude Tabone, D. Rouchon, Pascal Besson, S. Reboh
Publikováno v:
Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89e933226aaffad25a5bab6720dc2bf5
https://doi.org/10.7567/ssdm.2015.n-2-3
https://doi.org/10.7567/ssdm.2015.n-2-3
Autor:
M. Vinet, J.-M. Pedini, S. Becu, M. Collonge, T. Ernst, Bernard Previtali, M. Ribeiro, Gerard Ghibaudo
Publikováno v:
2009 International Symposium on VLSI Technology, Systems, and Applications.
For the first time, an analytical model of an Accumulation-Mode Suspended-Gate MOSFET is proposed. For very low power operation, adhesion energies of gate and gate oxide as low as 130µJ/m2 are required as well as sub-2.3N/m doubly clamped gate. Expe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b149078976fadd1e20d405b1a2729ba4
https://doi.org/10.1109/vtsa.2009.5159315
https://doi.org/10.1109/vtsa.2009.5159315
Autor:
Virginie Loup, Claudia Wiemer, Mikael Casse, Christine Morin, S. Minoret, Xavier Garros, Sandrine Lhostis, K. Dabertrand, Michele Perego, Vincent Cosnier, Pascal Besson, L. Vandroux, J-M. Pedini, Marco Fanciulli
Publikováno v:
Microelectronic engineering 84 (2007): 1886–1889.
info:cnr-pdr/source/autori:Cosnier, V; Besson, P; Loup, V; Vandroux, L; Minoret, S; Casse, M; Garros, X; Pedini, JM; Lhostis, S; Dabertrand, K; Morin, C; Wiemer, C; Perego, M; Fanciulli, M/titolo:Understanding of the thermal stability of the hafnium oxide%2FTiN stack via 2 'high k' and 2 metal deposition techniques/doi:/rivista:Microelectronic engineering/anno:2007/pagina_da:1886/pagina_a:1889/intervallo_pagine:1886–1889/volume:84
Microelectronic Engineering
Microelectronic Engineering, Elsevier, 2007, pp.Issue: 9-10, (2007) 1886-1889
Microelectronic Engineering, 2007, pp.Issue: 9-10, (2007) 1886-1889
info:cnr-pdr/source/autori:Cosnier, V; Besson, P; Loup, V; Vandroux, L; Minoret, S; Casse, M; Garros, X; Pedini, JM; Lhostis, S; Dabertrand, K; Morin, C; Wiemer, C; Perego, M; Fanciulli, M/titolo:Understanding of the thermal stability of the hafnium oxide%2FTiN stack via 2 'high k' and 2 metal deposition techniques/doi:/rivista:Microelectronic engineering/anno:2007/pagina_da:1886/pagina_a:1889/intervallo_pagine:1886–1889/volume:84
Microelectronic Engineering
Microelectronic Engineering, Elsevier, 2007, pp.Issue: 9-10, (2007) 1886-1889
Microelectronic Engineering, 2007, pp.Issue: 9-10, (2007) 1886-1889
In this work we evaluate the impact of the gate stack layers deposition technologies and their combination on the thermal stability of the stack with respect to EOT vs leakage figure of merit. Two HfO2 deposition technologies have been used: ALCVD an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f44cac09eaa12fc24fd69a1d8ecc4fc4
http://www.cnr.it/prodotto/i/1943
http://www.cnr.it/prodotto/i/1943