Zobrazeno 1 - 9
of 9
pro vyhledávání: '"J.-F. Lugand"'
Autor:
Hanako Okuno, T. Billon, J. F. Lugand, K. Yckache, S. Huet, L. Vandroux, Denis Mariolle, M. Fayolle, A. Fournier, J. Pontcharra, Viviane Muffato, P. Gautier, Jean Dijon, Etienne Quesnel, C. Jayet, H. Grampeix
Publikováno v:
Microelectronic Engineering. 88:833-836
Thanks to their outstanding electrical properties [1,2], carbon nanotubes (CNTs) are promising candidate to replace Cu in advanced interconnects [3-8]. In damascene based CNT via integration scheme, CNTs growth occurs on the whole surface of the wafe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e757d72c82472b9226ca3b338c86f767
https://doi.org/10.1016/j.mee.2010.07.038
https://doi.org/10.1016/j.mee.2010.07.038
Autor:
H. Achard, L. Ulmer, F. Ducroquet, M.E. Nier, S. Tedesco, F. Coudert, T. Farjot, J.-F. Lugand, M. Heitzmann, Simon Deleonibus, Y. Gobil, Bernard Previtali
Publikováno v:
IEEE Transactions on Electron Devices. 48:1816-1821
Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::609417f974aed9c290307a4a99e6799e
https://doi.org/10.1109/16.936712
https://doi.org/10.1109/16.936712
Publikováno v:
2011 IEEE International Interconnect Technology Conference.
This paper presents the integration of dense (2.5 1012 CNTs/cm2) Carbon Nanotubes in via structures for future microelectronic interconnects generations. Process steps performed after CNT growth in vias are studied. Two different CNT encapsulation la
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::000283bf411124bd876857cffb633b2d
https://doi.org/10.1109/iitc.2011.5940269
https://doi.org/10.1109/iitc.2011.5940269
Autor:
R. Anciant, N. Sillon, N. Bresson, P. Brianceau, J. F. Lugand, G. Pares, S. Minoret, V. Lapras
Publikováno v:
2011 IEEE International Conference on IC Design & Technology.
Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for fully integrated products such as SiP, SoP, 3D components integration (e.g memory stacking
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24cb25a0ebeaaa7a5d4ad53b1500179d
https://doi.org/10.1109/icicdt.2011.5783204
https://doi.org/10.1109/icicdt.2011.5783204
Autor:
G. Parès, N. Sillon, S. Huet, David Henry, S. Minoret, V. Lapras, Brendan Dunne, R. Anciant, J. F. Lugand
Publikováno v:
2009 11th Electronics Packaging Technology Conference.
Through Silicon Via (TSV) is a one of the more important bricks for 3D stacking and offer different integration approaches. The via-last approach has been first introduced into production. Yet the via-first approach is also currently actively investi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4aeea250200aef64e9ace862cb5db0d
https://doi.org/10.1109/eptc.2009.5416444
https://doi.org/10.1109/eptc.2009.5416444
Autor:
T. Farjot, F. Ducroquet, M.E. Nier, S. Tedesco, Bernard Previtali, Y. Gobil, M. Heitzmann, L. Ulmer, Simon Deleonibus, J.-F. Lugand, F. Coudert, H. Achard
Publikováno v:
30th European Solid-State Device Research Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3070f749415614370b460bf23ced4f90
https://doi.org/10.1109/essderc.2000.194801
https://doi.org/10.1109/essderc.2000.194801
Autor:
Francois Andrieu, A. Tiberj, B. Ghyselen, P. Leduc, J.M. Hartmann, Nicolas Daval, Y. Campidelli, Yves Morand, B. Blondeau, C. Lagahe-Blanchard, D. Bensahel, Vincent Paillard, J.-F. Lugand, Thomas Ernst, S. Pocas, Hubert Moriceau, Laetitia Vincent, O. Rayssac, Carlos Mazure, Cecile Aulnette, Alexandra Abbadie, Benedite Osternaud, A.-M. Cartier, Olivier Kermarrec, F. Fournel, N. Kernevez, I. Cayrefourq, Y. Bogumilowicz, M. Rivoire, C. Di Nardo, M.N. Séméria, Philippe Boucaud, Pascal Besson, Alain Claverie
Publikováno v:
Scopus-Elsevier
Strained Silicon On Insulator wafers are today envisioned as a natural and powerfulenhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, thisnew technology potentially combines enhanced devices scalability allowed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ed859ed97c4c5b94b8b997344e406b10
http://www.scopus.com/inward/record.url?eid=2-s2.0-19944432923&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-19944432923&partnerID=MN8TOARS
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Akademický článek
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