Zobrazeno 1 - 10
of 12
pro vyhledávání: '"J.-Ch. Barbe"'
Autor:
F. Tcheme Wakam, Gerard Ghibaudo, Sorin Cristoloveanu, M. Bawedin, Joris Lacord, J.-Ch. Barbe, Sebastien Martinie
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2019, pp.107732. ⟨10.1016/j.sse.2019.107732⟩
Solid-State Electronics, Elsevier, 2020, 168, pp.107731. ⟨10.1016/j.sse.2019.107731⟩
Solid-State Electronics, Elsevier, 2019, pp.107732. ⟨10.1016/j.sse.2019.107732⟩
Solid-State Electronics, Elsevier, 2020, 168, pp.107731. ⟨10.1016/j.sse.2019.107731⟩
In this work, we present a compact modeling of capacitorless A2RAM memory cell. It is obtained by combining A2RAM DC compact model with an equivalent circuit that mimics the memory state. The DC modeling is achieved by considering the A2RAM architect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::073fa69ed57bb13cc0ca748500df9b5f
https://hal.archives-ouvertes.fr/hal-02380158
https://hal.archives-ouvertes.fr/hal-02380158
Autor:
Maryline Bawedin, S. Cristoloveanu, F. Tcheme Wakam, Sebastien Martinie, J.-Ch. Barbe, Gerard Ghibaudo, Joris Lacord
Publikováno v:
EuroSOI-ULIS 2018
EuroSOI-ULIS 2018, Mar 2018, Granada, Spain
Solid-State Electronics
Solid-State Electronics, Elsevier, 2019, 159, pp.3-11. ⟨10.1016/j.sse.2019.03.038⟩
2018 EUROSOI-ULIS Proceedings
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Mar 2018, Granada, Spain. pp.1-4, ⟨10.1109/ULIS.2018.8354339⟩
Solid-State Electronics, 2019, 159, pp.3-11. ⟨10.1016/j.sse.2019.03.038⟩
HAL
EuroSOI-ULIS 2018, Mar 2018, Granada, Spain
Solid-State Electronics
Solid-State Electronics, Elsevier, 2019, 159, pp.3-11. ⟨10.1016/j.sse.2019.03.038⟩
2018 EUROSOI-ULIS Proceedings
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Mar 2018, Granada, Spain. pp.1-4, ⟨10.1109/ULIS.2018.8354339⟩
Solid-State Electronics, 2019, 159, pp.3-11. ⟨10.1016/j.sse.2019.03.038⟩
HAL
session 1: Fabrication and Process characterization; International audience; We propose for the first time a method based on C-V measurement to extract the bridge doping profile which governs the A2RAM performances. Assessed with TCAD simulation and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a578c67814303936f889e5d5f31d147c
https://hal-cea.archives-ouvertes.fr/cea-02270895
https://hal-cea.archives-ouvertes.fr/cea-02270895
Autor:
Sylvain Barraud, L. Bourdet, S. Martinia, Joris Lacord, Zaiping Zeng, François Triozon, Yann-Michel Niquet, P. Blaise, Olivier Rozeau, J.-Ch. Barbe
Publikováno v:
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2017, Kamakura, Japan. ⟨10.23919/SISPAD.2017.8085250⟩
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2017, Kamakura, Japan. ⟨10.23919/SISPAD.2017.8085250⟩
International audience; GAA nanowires (NW) transistors are promising candidates for sub 10 nm technology nodes. They offer optimal electrostatic control, thereby enabling ultimate CMOS device scaling. Horizontally stacked they are a natural extension
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c309ca030a91eddabafff68784318b7e
https://cea.hal.science/cea-01973405/file/5-Barbe_SISPAD2017.pdf
https://cea.hal.science/cea-01973405/file/5-Barbe_SISPAD2017.pdf
Publikováno v:
2017 SISPAD Proceedings
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2017, Kamakura, Japan. pp.329-332, ⟨10.23919/SISPAD.2017.8085331⟩
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2017, Kamakura, Japan. pp.329-332, ⟨10.23919/SISPAD.2017.8085331⟩
session: Future Devices (12.4); International audience; A2RAM belongs to the 1T-DRAM family and is a potential candidate to replace the traditional 1T/1C- DRAM [1-2]. In this paper, we propose a TCAD simulation [3] methodology to assess A2RAM perform
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8b74f7daca0035e2389e9823404da15a
https://hal.archives-ouvertes.fr/hal-02007238
https://hal.archives-ouvertes.fr/hal-02007238
Publikováno v:
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
UTBB-FDSOI device performance can be enhanced by stress engineering, especially thanks SiGe channel in pMOS [1]. SiGe channels induce strong local layout effects [2, 3] which are mainly due to stress relaxation during STI process [2]. In this study,
Autor:
Gerard Ghibaudo, Sorin Cristoloveanu, H. El Dirani, Yuan Taur, Sebastien Martinie, Kyung Hwa Lee, X. Mescot, Joris Lacord, J.-E. Broquin, Mukta Singh Parihar, Ph. Galy, M. Bawedin, Yong Tae Kim, Francisco Gamiz, Pascal Fonteneau, J-Ch. Barbe
Publikováno v:
Microelectronic Engineering
Microelectronic Engineering, Elsevier, 2017, 178, pp.245-249. ⟨10.1016/j.mee.2017.05.047⟩
HAL
20th International Conference on Insulating Films on Semiconductors (INFOS 2017)
20th International Conference on Insulating Films on Semiconductors (INFOS 2017), Jun 2017, Potsdam, Germany
Microelectronic Engineering, 2017, 178, pp.245-249. ⟨10.1016/j.mee.2017.05.047⟩
Microelectronic Engineering, Elsevier, 2017, 178, pp.245-249. ⟨10.1016/j.mee.2017.05.047⟩
HAL
20th International Conference on Insulating Films on Semiconductors (INFOS 2017)
20th International Conference on Insulating Films on Semiconductors (INFOS 2017), Jun 2017, Potsdam, Germany
Microelectronic Engineering, 2017, 178, pp.245-249. ⟨10.1016/j.mee.2017.05.047⟩
International audience; A systematic study of a capacitorless 1T-DRAM fabricated in 28 nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z2-FET memory cell features a large current sense margin and small OFF-s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8e3d61f1fe991f951c7211f88f2b242e
https://hal.archives-ouvertes.fr/hal-01948006
https://hal.archives-ouvertes.fr/hal-01948006
Autor:
Kyung Hwa Lee, Sebastien Martinie, Francisco Gamiz, X. Mescot, H. El Dirani, Ph. Galy, Binjie Cheng, Sorin Cristoloveanu, Carlos Navarro, Joris Lacord, M. Bawedin, Mukta Singh Parihar, C. Le Royer, Asen Asenov, Pascal Fonteneau, Yuan Taur, J.-Ch. Barbe
Publikováno v:
2017 EUROSOI-ULIS Proceedings
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.51-52, ⟨10.1109/ULIS.2017.7962598⟩
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.51-52, ⟨10.1109/ULIS.2017.7962598⟩
session 4: Memory Devices; International audience; We review the operation mechanisms of the Z 2 -FET underlining its attractiveness as a capacitorless DRAM memory. The main parameters that govern the memory performance are discussed based on systema
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3d01214c6b0e09a2af7b2e739a9089a8
https://hal.archives-ouvertes.fr/hal-02007047
https://hal.archives-ouvertes.fr/hal-02007047
Autor:
François Triozon, O. Rozeau, R. Coquand, S. Barraud, Joris Lacord, Sebastien Martinie, J.-Ch. Barbe, Yann-Michel Niquet, Claude Tabone, Thierry Poiroux, E. Augendre, O. Faynot, Maud Vinet
Publikováno v:
2016 IEEE International Electron Devices Meeting (IEDM)
2016 IEEE International Electron Devices Meeting (IEDM), Dec 2016, San Francisco, United States. ⟨10.1109/IEDM.2016.7838369⟩
2016 IEEE International Electron Devices Meeting (IEDM), Dec 2016, San Francisco, United States. ⟨10.1109/IEDM.2016.7838369⟩
International audience; In this work, a predictive and physical compact model for NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) MOSFET is presented. Based on a novel methodology for the calculation of the surface potential including quantum confin
Autor:
Kyung Hwa Lee, H. El Dirani, Sorin Cristoloveanu, Mukta Singh Parihar, J.-Ch. Barbe, Jing Wan, Yong Tae Kim, X. Mescot, Sebastien Martinie, Yuan Taur, Francisco Gamiz, Pascal Fonteneau, Yong Xu, Ph. Galy, Binjie Cheng, M. Bawedin, M. Duan, C. Le Royer, Fikru Adamu-Lema, Carlos Navarro, Joris Lacord, Asen Asenov
Publikováno v:
Solid-State Electronics
Solid-State Electronics, 2018, 143, pp.10-19. ⟨10.1016/j.sse.2017.11.012⟩
Solid-State Electronics, Elsevier, 2018, 143, pp.10-19. ⟨10.1016/j.sse.2017.11.012⟩
Solid-State Electronics, 2018, 143, pp.10-19. ⟨10.1016/j.sse.2017.11.012⟩
Solid-State Electronics, Elsevier, 2018, 143, pp.10-19. ⟨10.1016/j.sse.2017.11.012⟩
International audience; The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments an
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