Zobrazeno 1 - 10
of 26
pro vyhledávání: '"J. Yetter"'
Publikováno v:
Journal of Aircraft. 35:106-112
An analytical and experimental description of how the fan exhaust of a modern turbofan can be dee ected into an annular cascade using only core bleed e ow is presented. Thrust reversing, emphasized herein, and/or vectoring is achieved without the nee
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b92d5c9a8f2664a7c8c6daa3477d8ba8
https://doi.org/10.2514/2.2266
https://doi.org/10.2514/2.2266
Publikováno v:
IEEE Micro. 13:22-35
The PA7100 CPU, the first precision-architecture, reduced-instruction-set-computer (PA-RISC) architecture implementation to combine an integer core and floating-point coprocessor into a single-chip format, is described. It incorporates superscalar ex
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8eef1af4efb468e0d5c6022ab8b21e54
https://doi.org/10.1109/40.216746
https://doi.org/10.1109/40.216746
Publikováno v:
IEEE Spectrum. 28:58-62
The process employed by a group of workstation designers in creating a prototype for a high-performance, low-cost workstation is described. The design team moved an existing architecture-the precision-architecture, reduced-instruction-set computer (P
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa0c1cafd88e58435fb4893ca9d44382
https://doi.org/10.1109/6.76303
https://doi.org/10.1109/6.76303
Publikováno v:
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
A Reduced Instruction Set Computer using direct hardware instruction decode and 3-stage pipelined execution will be described. At an operating frequency of 30MHz, a 120Mbytes/s transfer rate on an external cache/coprocessor interface is achieved. NMO
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::913e876866ed256cd3c8cbd1d9c1f215
https://doi.org/10.1109/isscc.1987.1157220
https://doi.org/10.1109/isscc.1987.1157220
Publikováno v:
1992 Symposium on VLSI Circuits Digest of Technical Papers.
A RISC CPU chip has been designed for 100-MHz operation. The chip combines a 32-b integer core and a full 64-b floating point coprocessor on a 1.43-cm*1.43-cm die. The chip is fabricated in a 0.8- mu m CMOS process with three layers of aluminum inter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c88cb36a2ddf79ff17b51c1051a162e8
https://doi.org/10.1109/vlsic.1992.229260
https://doi.org/10.1109/vlsic.1992.229260
Publikováno v:
Compcon
A novel low-cost, high-performance RISC (reduced instruction set computer) processor chip set implementing Hewlett Packard's PA-RISC instruction set has been developed. The design consists of a CPU chip containing 577 K transistors implemented in HP'
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::48b5079396fe4a1fe9b882f7d77b6d56
https://doi.org/10.1109/cmpcon.1991.128807
https://doi.org/10.1109/cmpcon.1991.128807
Publikováno v:
33rd Joint Propulsion Conference and Exhibit.
An analytical and experimental description of how the fan exhaust of a modern turbofan can be dee ected into an annular cascade using only core bleed e ow is presented. Thrust reversing, emphasized herein, and/or vectoring is achieved without the nee
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b230105f46cd43a31f86122611b960d0
https://doi.org/10.2514/6.1997-3152
https://doi.org/10.2514/6.1997-3152
Autor:
T. Williams, L. Madden, J. Slager, L. Heller, K. Gudger, D.J. Allstot, J. Yetter, C. Svensson
Publikováno v:
1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
A summary on competing CMOS circuit techniques is presented. It is noted that, when the complete picture is examined (including gating, clocking, and testability), much more disagreement than agreement is evident among CMOS designers. The panel probe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20cbbe2a4fa0c5ff041a4077c0f6cf2c
https://doi.org/10.1109/isscc.1993.280075
https://doi.org/10.1109/isscc.1993.280075
Publikováno v:
Open-File Report.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0704521b4ed25e2ebe9d20672f1d3b97
https://doi.org/10.3133/ofr92446
https://doi.org/10.3133/ofr92446
Autor:
Michael A Buckley, Craig A. Gleason, D. Hollenbeck, Richard J. Luebs, K. Erskine, Joel D. Lamb, B. Long, J. Wheeler, S. McMullen, J. Yetter, C. Kohlhardt, H. Hill, Daniel L Halperin, Jonathan P Lotz, Robert J. Horning, Patrick Knebel, R. Novak, Darius Tanksalvala, H. Tran, L. Sigel, C. Simpson, Doug Quarnstrom, Donald Kipp, John R. Spencer, S. Chapin, Eric Delano, Duncan Weir, E. Rashid, Thomas R. Hotchkiss, M. Forsyth, T. Gaddis
Publikováno v:
1990 37th IEEE International Conference on Solid-State Circuits.
A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both comme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a72489e0852fc0c8239643d7019fe6b
https://doi.org/10.1109/isscc.1990.110125
https://doi.org/10.1109/isscc.1990.110125