Zobrazeno 1 - 10
of 76
pro vyhledávání: '"J. Versluijs"'
Autor:
Philippe Leray, N. Jourdan, O. Varela Pedreira, E. Dentoni-Litta, Thomas Witters, Werner Gillijns, Nancy Heylen, L. Ramakers, E. Grieten, Zaid El-Mekki, Gayle Murdoch, V. Vega-Gonzalez, Anne-Laure Charley, Ivan Ciofi, Zsolt Tokei, H. Vats, S. V. Gompel, M. H. van der Veen, L. Halipre, J. Swerts, A. Haider, Bilal Chehab, S. Park, N. Bazzazian, Quoc Toan Le, B. De Wachter, T. Peissker, Harinarayanan Puliyalil, Naoto Horiguchi, Miroslav Cupak, J. Versluijs, G. T. Martinez, Y. Kimura, R. Kim, J. Geypen, J. Uk-Lee, N. Nagesh, D. Montero, L. Rynders, M. Ercken, D. Batuk, K. Croes, Patrick Verdonck, Manoj Jaysankar, Y. Drissi, T. Webers
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::775097fabe7d875876eeac9844668bb1
https://doi.org/10.1109/iitc51362.2021.9537535
https://doi.org/10.1109/iitc51362.2021.9537535
Autor:
Zaid El-Mekki, F. Schleicher, Frederic Lazzarino, D. Trivkovic, Zsolt Tokei, B. De-Wachter, S. V. Gompel, L. Halipre, E. Vancoille, S. Decoster, G. Muroch, Thomas Witters, L. Dupas, O. Varela-Pereira, B. Briggs, Quoc Toan Le, Harinarayanan Puliyalil, Christopher J. Wilson, Philippe Leray, N. Jourdan, I. Demonie, C. Lorant, Joost Bekaert, Nancy Heylen, Y. Kimura, Rogier Baert, M. H. van der Veen, J. Versluijs, Miroslav Cupak, Patrick Verdonck, K. Croes, Manoj Jaysankar, Anne-Laure Charley, J. Heijlen, J. Uk-Lee, Ivan Ciofi, Y. Drissi, V. Vega-Gonzalez, S. Paolillo, H. Vats, D. Montero, L. Rynders, Els Kesters, M. Ercken, A. Lesniewska, R. Kim, Lieve Teugels, T. Webers
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d5b5a73112c7be6f5016d4aa4c44eb7
https://doi.org/10.1109/iedm13553.2020.9372096
https://doi.org/10.1109/iedm13553.2020.9372096
Autor:
Nancy Heylen, K. Croes, Rogier Baert, S. Park, Geoffrey Pourtois, Jean-Philippe Soulie, Katia Devriendt, Christopher J. Wilson, Ming Mao, Q-T. Le, V. Blanco, Gayle Murdoch, Herbert Struyf, Anshul Gupta, V. Vega, Lieve Teugels, S. Paolillo, N. Jourdan, Kiroubanand Sankaran, J. Sweerts, Ivan Ciofi, S. Decoster, P. Morin, Els Kesters, Juergen Boemmels, Frederic Lazzarino, Zs. Tokei, Christoph Adelmann, M. H. van der Veen, M. Ercken, Kris Vanstreels, S. Van Elshocht, M. O'Toole, J. Versluijs, M. H. Na, Frank Holsteyns, Houman Zahedmanesh
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3b4b449b819b2556b63b50762bf16b9
https://doi.org/10.1109/iedm13553.2020.9371903
https://doi.org/10.1109/iedm13553.2020.9371903
Autor:
V. Vega-Gonzalez, J. Bekaert, E. Kesters, Q. T. Le, C. Lorant, O. Varela P., L. Teugels, N. Heylen, Z. El-Mekki, M. van der Veen, T. Webers, C. J. Wilson, H. Vats, L. Rynders, M. Cupak, J. Uk-Lee, Y. Drissi, L. Halipre, A.-L. Charley, P. Verdonck, T. Witters, S. V. Gompel, B. Briggs, Y. Kimura, N. Jourdan, I. Ciofi, A. Gupta, A. Contino, G. Boccardi, S. Lariviere, L. Dupas, B. De-Wachter, E. Vancoille, S. Decoster, F. Lazzarino, M Ercken, P. Debacker, R. Kim, D. Trivkovic, K. Croes, P. Leray, L. Dillemans, Y.-F. Chen, Z. Tokei, J. Versluijs, A. Lesniewska, S. Paolillo, R. Baert, H. Puliyalil
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7eecb12b8a386042eac7e3255fe54876
https://doi.org/10.1109/iedm19573.2019.8993538
https://doi.org/10.1109/iedm19573.2019.8993538
Autor:
E. Vancoille, T. Huynh-Bao, Vasile Paraschiv, E. Vecchio, Eddy Simoen, Jeroen E. Scheerder, Erik Rosseel, Anabela Veloso, Hugo Bender, J. Versluijs, Lieve Teugels, Geert Eneman, W. Li, Boon Teik Chan, Roger Loo, Adrian Chasin, D. Radisic, Farid Sebaai, Andriy Hikavyy, Claudia Fleischmann, Naoto Horiguchi, Philippe Matagne, Katia Devriendt, Stephan Brus, Paola Favia
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
We report on p and n-type vertical gate-all-around (GAA) nanowire (NW) and nanosheet (NS) FETs which offer attractive opportunities for ultra-scaled circuits. An in-depth evaluation is presented on the impact of doping and key device dimensions to im
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c0575814d1d830065df4a297be4eca1
https://doi.org/10.1109/iedm19573.2019.8993602
https://doi.org/10.1109/iedm19573.2019.8993602
Autor:
V. Peña, Romain Ritzenthaler, D. Jang, X. Zhou, G. Mannaert, T. Miyashita, A. Oliveira, K. Kenis, A. Veloso, Gaetano Santoro, Adrian Chasin, Farid Sebaai, Lin Yongjing, J. Machillot, K. Devriendt, Eddy Simoen, Naoto Horiguchi, Naomi Yoshida, T. Hopf, O. Richard, Hans Mertens, S.-C. Chen, J. Versluijs, Min-Soo Kim
Publikováno v:
Extended Abstracts of the 2019 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7a83132858be492f12351a8df63aa80a
https://doi.org/10.7567/ssdm.2019.n-1-03
https://doi.org/10.7567/ssdm.2019.n-1-03
Autor:
B. Briggs, S. Guissi, C.J. Wilson, J. Ryckaert, S. Paolillo, K. Vandersmissen, J. Versluijs, C. Lorant, N. Heylen, J. Boemmels, Z. Tokei, Y. Sherazi, P. Weckx, L. Kljucar, M.VanDer Veen, G. Boccardi, V. DeHeyn, A. Gupta, J. Ervin, M. Kamon
Publikováno v:
Extended Abstracts of the 2018 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01ce6d5919932daabf5e3aa91acb3ee1
https://doi.org/10.7567/ssdm.2018.g-3-02
https://doi.org/10.7567/ssdm.2018.g-3-02
Replacement Metal Contact Using Sacrificial ILD0 for Wrap Around Contact in Scaled FinFET Technology
Autor:
Katia Devriendt, T. Hopf, Naoto Horiguchi, Antoine Pacco, Lieve Teugels, Dan Mocuta, Steven Demuynck, E. Altamirano Sanchez, Christa Vrancken, A. Dangol, S-A. Chew, Liping Zhang, J. Versluijs
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
In this work, we propose replacement metal contact (RMC) flow by using sacrificial ILD0 that is suitable for wrap around contact (WAC). RMC minimize erosion of gate plug, spacer and S/D area at scaled contact formation. The concept of the flow has be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e945735d2e79e50029eb0cf269757b4
https://doi.org/10.1109/iitc.2018.8430457
https://doi.org/10.1109/iitc.2018.8430457
Autor:
O. Varela Pedreira, Danny Wan, Nancy Heylen, Zs. Tokei, S. Decoster, K. Croes, Farid Sebaai, N. Jourdan, S. Paolillo, Katia Devriendt, B. Briggs, Els Kesters, S. Lariviere, Christopher J. Wilson, J. Versluijs, Zaid El-Mekki, Jürgen Bömmels, Julien Ryckaert, Shibesh Dutta, Arindam Mallik, Patrick Verdonck, M. H. van der Veen
Publikováno v:
2017 IEEE International Interconnect Technology Conference (IITC).
We demonstrate an integration approach to enable 16nm half-pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho-Etch (LE3) and tone-inversion. A silicon-verified DOE experiment on a SAQP proce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1475a3b5e3e3395e1268a797b319ed19
https://doi.org/10.1109/iitc-amc.2017.7968983
https://doi.org/10.1109/iitc-amc.2017.7968983
Autor:
Erik Rosseel, Julien Ryckaert, E. Vecchio, W. Li, Philippe Matagne, Katia Devriendt, M. Ercken, J. Versluijs, Anabela Veloso, Stephan Brus, C. Delvaux, Z. Tao, Vasile Paraschiv, Nadine Collaert, Boon Teik Chan, Dan Mocuta, Niamh Waldron, Efrain Altamirano-Sanchez, T. Huynh-Bao
Publikováno v:
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells wit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ef539062f48cee934246624d382a7b5
https://doi.org/10.1109/s3s.2016.7804409
https://doi.org/10.1109/s3s.2016.7804409