Výsledky vyhledávání

Experimental and analytical investigation of single event, multiple bit upsets in poly-silicon load, 64 K*1 NMOS SRAMs

Autor: W. A. Kolasinski, R.C. Martin, R. Koga, Nasr M. Ghoniem, Y. Song, Jon V. Osborn, K. N. Vu, J.H. Elder, J. S. Cable, A.A. Witteles

Publikováno v: IEEE Transactions on Nuclear Science. 35:1673-1677

Long time constants associated with extremely high pull-up resistances commonly used in high-density, polysilicon-load NMOS SRAMs were identified as the primary cause of single-event-induced, multiple-bit upsets recently observed in cyclotron tests.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::50e37a4d25e9387e9f579b608ba9663a
https://doi.org/10.1109/23.25520

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The Size Effect of Ion Charge Tracks on Single Event Multiple-Bit Upset

Autor: R.C. Martin, J. S. Cable, Y. Song, Nasr M. Ghoniem

Publikováno v: IEEE Transactions on Nuclear Science. 34:1305-1309

Double-bit upset rates in satellite memory cells as high as several percent of total upsets have recently been reported. This significant fraction may be explained by cosmic ion track sizes which are larger than previously postulated. Generation and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1f57acf493161dcfa021d09117d3c18d
https://doi.org/10.1109/tns.1987.4337470

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The Dependence of Latch-Up Sensitivity on Layout Features in CMOS Integrated Circuits

Autor: K. N. Vu, A. A. Witteles, Y. Song, J. S. Cable

Publikováno v: IEEE Transactions on Nuclear Science. 33:1493-1498

The separated source-to-substrate/well contact diffusion layout commonly used in CMOS IC design has been identified as a primary cause for latch-up sensivity in bulk CMOS devices. FXR testing as well as electrical characterization of latch-up has bee

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a005acd23fde09abdd2ae3d50be0eb11
https://doi.org/10.1109/tns.1986.4334629

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Parametric investigation of latch-up sensitivity in 1.25 μm CMOS technology

Autor: Y. Song, A. R. Coulson, A. M. Miscione, K. N. Vu, J. S. Cable, S. C. Lizotte

Publikováno v: IEEE Transactions on Nuclear Science. 34:1431-1437

The dependence of latch-up sensitivity in 1.25 μm p-well, CMOS devices on layout parameters, backside contacts, and thickness of epitaxial layers has been investigated by analysis and testing using a specially designed test chip. Retrograde wells an

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7c77d433f671000cddb224a52eb9f012
https://doi.org/10.1109/tns.1987.4337493

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Validation of Latch-Up Mitigation in Complex VLSI Circuits

Autor: J. S. Cable, D. C. Lee, J. A. Criscuolo

Publikováno v: IEEE Transactions on Nuclear Science. 33:1510-1514

FXR testing, circuit simulation, and computer automated design rule checks (DRCs) have been performed to validate the mitigation techniques used for latch-up protection of non-epi TRW devices. Innovative modification of DRC software has been speciall

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::016506e1701f7d653fd1538357d37db1
https://doi.org/10.1109/tns.1986.4334632

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Verifiticion of a SEU Model for Advanced 1-um CMOS Structures Using Heavy Ions

Autor: J. R. Carter, A. A. Witteles, J. S. Cable

Publikováno v: IEEE Transactions on Nuclear Science. 33:1586-1589

Modeling and test repsults are reported for TRW 1-um CMOS circuits. Excellent agreement between prediction And both Cyclotron and Californium testing has been obtained, and the results indicate that acceptable SEU error rates; can be achieved with a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::efa383649ed57fa90bee63c8df178c1c
https://doi.org/10.1109/tns.1986.4334646

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