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pro vyhledávání: '"J. Otterstedt"'
Akademický článek
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Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 6:284-291
The architecture and implementation of a programmable video signal processor dedicated as building block of a multiple instruction multiple data (MIMD)-based bus-connected multiprocessor system is presented. This system can either be constructed from
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b8a40d455768d39676d26b94f4bd864
https://doi.org/10.1109/92.678889
https://doi.org/10.1109/92.678889
Autor:
R. Allinger, K. Hofmann, Christian Peters, Mihail Jefremow, Doris Schmitt-Landsiedel, O. Bahlous, W. Allers, J. Otterstedt, S. Kassenetter, Thomas Kern
Publikováno v:
ISSCC
Spin-torque-transfer (STT) MRAM is a promising candidate for embedded non-volatile memory in next generation microcontrollers, because of superior endurance, low process costs and logic supply voltage operation. Two major drawbacks of STT-MRAM techno
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05c76096663ea66ebc6829293c263ecd
https://doi.org/10.1109/isscc.2013.6487706
https://doi.org/10.1109/isscc.2013.6487706
Publikováno v:
IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C. 19:105-109
A 16.6 cm/sup 2/ monolithic large-area integrated multiprocessor system comprising nine identical programmable video signal processing elements was reconfigured by excimer laser-formed connections and discontinuities of conductor lines in a redundant
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f00b0f84193a41f37ca254ba908020d9
https://doi.org/10.1109/3476.507146
https://doi.org/10.1109/3476.507146
Akademický článek
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Publikováno v:
[1992] Proceedings International Conference on Wafer Scale Integration.
A defect-tolerant large area integrated circuit 16 cm/sup 2/ in size was implemented. It contains the test and configuration frame for a MIMD (multiple instruction, multiple data) multiprocessor architecture for video signal processing. The emphasis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::729948e85180fd81b1216d4de8754a14
https://doi.org/10.1109/icwsi.1992.171793
https://doi.org/10.1109/icwsi.1992.171793
Publikováno v:
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon.
In this paper, an efficient method for self-test and self-reconfiguration for a word-oriented single-port static RAM is presented. First, a suitable test algorithm is chosen and implemented as a built-in self-test (BIST) with low area overhead. Furth
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30047fb6b2eba8032744a0ab94d20378
https://doi.org/10.1109/iciss.1996.552419
https://doi.org/10.1109/iciss.1996.552419
Publikováno v:
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon.
A 16.6 cm/sup 2/ monolithic large area integrated multiprocessor system comprising 9 identical programmable video signal processing elements was reconfigured by excimer laser formed connections and discontinuities of conductor lines in a redundant bu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5c75210636917c59796656ed9cc0ca7
https://doi.org/10.1109/iciss.1996.552417
https://doi.org/10.1109/iciss.1996.552417
Publikováno v:
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon.
In this paper we introduce a large area integrated circuit (LAIC) called MAXPE9 which integrates 9 programmable video signal processing elements (PEs) on an area of 16.6 cm/sup 2/. Each PE has a peak arithmetic performance of 1 giga operations per se
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6f4cf5f6ea0c973f07d7ee9332999f7
https://doi.org/10.1109/iciss.1996.552418
https://doi.org/10.1109/iciss.1996.552418
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
The 16.6 cm/sup 2/ integrated circuit (LAIC) integrates a MIMD based multiprocessor system for real-time video coding applications (H.261, MPEG-1 and MPEG-2) that consists of identical bus-connected processing elements (PEs). Each PE contains a RISC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b46219ff9a979bd256932ee972d44301
https://doi.org/10.1109/isscc.1996.488630
https://doi.org/10.1109/isscc.1996.488630