Zobrazeno 1 - 10
of 28
pro vyhledávání: '"J. Othmer"'
Publikováno v:
Land, Vol 11, Iss 7, p 957 (2022)
The Rhenish lignite mining region is facing enormous structural changes due to the withdrawal from opencast mining. The current planning of the regional transformation process, however, has so far only insufficiently considered the local impacts of c
Externí odkaz:
https://doaj.org/article/fb04d58a90274a7abacc18243f7343bd
Autor:
Ting-Ping Liu, Meng-Lin Yu, J. Othmer, Fadi Saibi, Jenshan Lin, Titus Huang, E. Sackinger, Jinghong Chen, Fuji Yang, Kameran Azadet
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:1876-1893
The feasibility of a 40 Gb/s subcarrier modulated optical transmission system using low-cost optoelectronic components and CMOS IC technology is presented. The optical channel impairments are studied. A complete DSP framework is developed to cancel o
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:1813-1821
This paper presents an 8-channel 2.5–3.125-Gb/s/ch serial link transceiver that achieves a total IO bandwidth of 20 Gb/s with a power consumption of less than 685 mW. The macrocell uses a shared phase-locked loop (PLL) architecture to minimize the
Autor:
J. Sweet, Chris Nicol, Asawaree Kalavade, J. Williams, Christopher J. Terman, S.J. Daubert, E. Micca, Kanwar Jit Singh, Bryan D. Ackland, E. Sackinger, M. Moturi, D. Brinthaupt, Jay Henry O'neill, J. Othmer, A. Anesko, J. Knobloch
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:412-424
An MIMD multiprocessor digital signal-processing (DSP) chip containing four 64-b processing elements (PE's) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a
Autor:
Jinghong Chen, Fadi Saibi, Ting-Ping Liu, J. Othmer, Fuji Yang, Meng-Lin Yu, Kamran Azadet, Jenshan Lin, Titus Huang, E. Sackinger
Publikováno v:
CICC
The feasibility of a 40Gb/s subcarrier modulated optical transmission system using low-cost optoelectronic components and CMOS IC technology is presented. To validate that the 40Gb/s system can be implemented in CMOS, an integrated QAM-16 transceiver
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
An 8-channel serial link transceiver realizes 20 Gb/s full duplex total I/O throughput with
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
Autor:
B. Ackland, A. Anesko, D. Brinthaupt, S.J. Daubert, A. Kalavade, J. Knobloch, E. Micca, M. Moturi, C.J. Nicol, J.H. O'Neill, J. Othmer, E. Sackinger, K.J. Singh, J. Sweet, C.J. Terman, J. Williams
Publikováno v:
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
This single-chip audio/video processor (AVP) performs all necessary data and signal processing for H.320 (ISDN) and H.324 (POTS) video conferencing (up to CIF (352/spl times/288) at 30 frames/s, simultaneous encode/decode), simultaneous MPEG1 audio (
Autor:
Neil Weste, Christopher J. Terman, L. Letham, B. Edwards, R. Spiwak, D. Brinthaupt, V. Maheshwari, J. Othmer
Publikováno v:
1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
A 450-MOPS video decoder that decompresses both H.261 and MPEG (Motion Picture Experts Group) compressed video streams is described. The decoder accepts bit rates up to 4 Mb/s and provides decoded frames of up to 352*288 pixels (CIF) at up to 30 fram