Investigation on threshold voltage instability under sweeping and DC gate bias stressing of SiC symmetrical and asymmetrical double-trench MOSFETs

Autor: J. Yang, S. Jahdi, B. Stark, J. Ortiz-Gonzalez, R. Wu, O. Alatise, P. Mellor

Publikováno v: Yang, J, Jahdi, S, Stark, B H, Ortiz-Gonzalez, J, Wu, R, Alatise, O & Mellor, P H 2022, Investigation on threshold voltage instability under sweeping and DC gate bias stressing of SiC symmetrical and asymmetrical double-trench MOSFETs . in 11th International Conference on Power Electronics, Machines and Drives (PEMD 2022) . Institution of Engineering and Technology (IET), Newcastle, UK, pp. 301-307, 11th International Conference on Power Electronics, Machines and Drives (PEMD 2022), Newcastle, United Kingdom, 21/06/22 . https://doi.org/10.1049/icp.2022.1066

In this paper, measurements on gate threshold voltage drift by sweeping the gate voltage and both with positive and negative DC gate stressing are performed on symmetrical and asymmetrical double-trench SiC MOSFETs with comparison to SiC planar MOSFE

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::296e2b6f40bdc55a3f40d5f111c9d7b7
https://research-information.bris.ac.uk/en/publications/584467c7-5032-44b0-8940-2a38655389ae

Optimisation of the gate voltage in SiC MOSFETS: efficiency vs reliability

Autor: Xiang Wang, Volker Pickert, Ruizhu Wu, Haimeng Wu, Olayiwola Alatise, J. Ortiz Gonzalez, Philip Mawby

This paper presents a comprehensive study of the impact of the gate voltage on the switching and ON-state performance of SiC MOSFETs. It is well known that the gate oxide in SiC MOSFETs is not as reliable as that in silicon MOSFETs due to increased f

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7890119ebcf768753f3a93d656295f82
https://nrl.northumbria.ac.uk/id/eprint/45606/1/PEMD2020_Full_paper_OPTIMISATION_OF_THE_GATE_VOLTAGE_IN_SiC_MOSFETS.pdf

UIS performance and ruggedness of stand-alone and cascode SiC JFETs

Autor: S.N. Agbo, Olayiwola Alatise, Saeed Jahdi, Ruizhu Wu, J. Ortiz Gonzalez

Publikováno v: Agbo, S N, Ortiz Gonzalez, J, Wu, R, Jahdi, S & Alatise, O 2020, ' UIS performance and ruggedness of stand-alone and cascode SiC JFETs ', Microelectronics Reliability, vol. 114, 113803 . https://doi.org/10.1016/j.microrel.2020.113803

In this paper the ruggedness of stand-alone and cascode SiC JFETs is evaluated under single and repetitive unclamped inductive switching (UIS). The impact of the JFET gate resistance, avalanche current and temperature are evaluated. The results show

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::050f0428a8ffd4c53a1c596ac08a962f
http://wrap.warwick.ac.uk/143999/1/WRAP-UIS-performance-ruggedness-stand-alone-cascode-SiC-JFETs-Alatise-2020.pdf

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Challenges of Junction Temperature Sensing in SiC Power MOSFETs

Autor: J. Ortiz Gonzalez, Olayiwola Alatise

Publikováno v: 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia).

Junction temperature sensing is an integral part of both on-line and off-line condition monitoring where direct access the bare die surface is not available. Given a defined power input, the junction temperature enables the estimation of the junction

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5d21cd529756431c84b5cf729da80ca9
https://doi.org/10.23919/icpe2019-ecceasia42246.2019.8797281