Zobrazeno 1 - 10
of 65
pro vyhledávání: '"J. L. Ogier"'
Publikováno v:
Microelectronic Engineering. 109:168-171
Display Omitted A statistics method of parametric measurement enabled the characterization of hump effect.With TCAD simulation in three dimensions, hump effect can be put in evidence.Hump effect can be suppressed by a MOSFET layout modification witho
Autor:
L. Truphemus, Pascal Masson, Pascal Fornara, François H. Julien, J-M. Portal, Y. Bert, Y. Joly, Hassen Aziza, J.-L. Ogier, L. Lopez
Publikováno v:
IEEE Transactions on Electron Devices. 60:1263-1267
On CMOS technology, some process steps can create a parasitic phenomenon named “hump effect.” This parasitic effect can have a strong impact on gate voltage matching of differential pairs and, as a consequence, on analog circuit performances. In
Autor:
G. Molas, G. Just, J.-L. Ogier, Arnaud Regnier, L. Masoero, Jérémy Postel-Pellerin, Roberto Simola, V. Della Marca, F. Lalande, Stephan Niel
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2013, 79, pp.210-217. ⟨10.1016/j.sse.2012.09.001⟩
Solid-State Electronics, 2013, 79, pp.210-217. ⟨10.1016/j.sse.2012.09.001⟩
Solid-State Electronics, Elsevier, 2013, 79, pp.210-217. ⟨10.1016/j.sse.2012.09.001⟩
Solid-State Electronics, 2013, 79, pp.210-217. ⟨10.1016/j.sse.2012.09.001⟩
International audience; In this paper the consumption of Flash Floating Gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to
Autor:
R. Laffont, Gilles Micolau, Arnaud Regnier, J. Melkonian, J.-L. Ogier, Jérémy Postel-Pellerin, R. Djenadi, F. Lalande, P. Chiquet
Publikováno v:
Solid-State Electronics. 78:80-86
This work is devoted to an original experimental method based on a classical data retention performed under a continuous gate stress. The method proposed here allows to discriminate the possible leakage paths in a non-volatile electrical memory array
Publikováno v:
Solid-State Electronics. 78:151-155
This paper shows how floating gate (FG) memory cells behavior during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at High or Low Temperature Bake (HTB or LTB respectively) to provid
Publikováno v:
2014 International Semiconductor Conference (CAS)
2014 International Semiconductor Conference (CAS), Oct 2014, Sinaia, France. ⟨10.1109/SMICND.2014.6966433⟩
2014 International Semiconductor Conference (CAS), Oct 2014, Sinaia, France. ⟨10.1109/SMICND.2014.6966433⟩
International audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::878b910082f26a11194c4b5b8ad76a8a
https://hal.archives-ouvertes.fr/hal-01760566
https://hal.archives-ouvertes.fr/hal-01760566
Publikováno v:
2014 IEEE International Integrated Reliability Workshop Final Report (IIRW).
In this paper, gate stress at high electrical field has been studied on High Voltage MOSFETs used for Non-Volatile Memory applications. Charge pumping measurements and characteristic Capacitance-Voltage have been applied to demonstrate that degradati
Publikováno v:
2014 29th Symposium on Microelectronics Technology and Devices (SBMicro).
In this paper, analog and digital low-voltage MOSFETs having the gate contact over Shallow Trench Isolation (reference layout) or over active area (innovative layout) are studied. Using electrical parameters measurements, Linear Ramp Voltage Stress a
Publikováno v:
Microelectronics Reliability
Microelectronics Reliability, 2014, 54 (9-10), pp.2262-2265. ⟨10.1016/j.microrel.2014.07.063⟩
Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2262-2265. ⟨10.1016/j.microrel.2014.07.063⟩
Microelectronics Reliability, 2014, 54 (9-10), pp.2262-2265. ⟨10.1016/j.microrel.2014.07.063⟩
Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2262-2265. ⟨10.1016/j.microrel.2014.07.063⟩
In this paper the impact of the endurance degradation on the programming window and the energy consumption of flash floating gate memories is investigated. Using a new measurement technique we characterized the evolution of the dynamic drain current
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ed0794ed2eafc7eb7ae6677ce02b7221
https://hal.science/hal-01760459
https://hal.science/hal-01760459
Publikováno v:
2014 IEEE International Conference on Electron Devices and Solid-State Circuits.
In this paper, gate stress has been studied on High Voltage p- and n-MOSFETs used for Non-Volatile Memory applications. For the first time, a higher degradation on n-channel transistor compared to p-channel transistor has been observed. Time dependen