Zobrazeno 1 - 10
of 245
pro vyhledávání: '"J. Klais"'
Autor:
J. Klais, Hartmut Ruelke, G. Grasshoff, Srikanteswara Dakshina-Murthy, Martin Mazur, Karla Romero, Katja Huy, Marilyn I. Wright, Scott A. Bell, Rolf Stephan, Sarah N. McGowan
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 18:539-545
A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to
Autor:
D. Greenlaw, Jon D. Cheek, Manfred Horstmann, Christoph Schwan, Markus Lenski, Peter Huebler, Scott Luning, R. van Bentum, N. Kepler, Matthias Schaller, James F. Buller, Hartmut Ruelke, Kai Frohberg, Gert Burbach, Rolf Stephan, J. Klais, S. Krishnan, Jörg Hohage, Andy Wei, Th. Feudel, Michael Raab, G. Grasshoff, Karsten Wieczorek, Martin Gerhardt
Publikováno v:
Materials Science and Engineering: B. :3-8
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI t
Autor:
Peter Javorka, Casey Scott, D. Greenlaw, Andreas Gehring, B. Mulfinger, Markus Lenski, H. Geisler, Anthony Mowry, T. Mantei, Guido Koerner, Manfred Horstmann, Maciej Wiatr, Katja Huy, Roman Boschke, J. Klais, Ralf Otterbach, Andy Wei
Publikováno v:
2007 International Semiconductor Device Research Symposium.
Stress engineering has become the sine qua non of any advanced CMOS technology since the 90nm technology node. In this paper, we focus on the influence of material properties and anneal sequences on the benefit of the stress-memorization technique fo
Autor:
John A. Fitzsimmons, Vincent J. McGahay, K. Malone, M. Minami, Siddhartha Panda, Manfred Horstmann, A. Wei, Helmut Bierstedt, H. Nii, A. Waite, A. Sakamoto, Michael A. Gribelyuk, M. Cullinan-Scholl, D. Harmon, A. Hellmich, M. Kiene, Patrick Press, Hartmut Ruelke, H. Zhu, H. Chen, H. Nakayama, Anthony G. Domenicucci, G. Sudo, Henry A. Nye, P. Fisher, Hans-Jürgen Engelmann, H. VanMeer, M. Newport, X. Chen, Tenko Yamashita, Cathryn Christiansen, Hasan M. Nayfeh, Dureseti Chidambarrao, Guido Koerner, Christopher D. Muzzy, S.-F. Huang, Ralf Otterbach, David M. Fried, J. Kluth, Jörg Hohage, M. Trentsch, I. Peidous, Thorsten Kammler, Mukesh Khare, Dominic J. Schepis, K. Rim, Spooner Terry A, K. Miyamoto, P.V. McLaughlin, Michael Raab, T. H. Ivers, Dan Mocuta, D.R. Davies, Jason Gill, Scott Luning, Woo-Hyeong Lee, Gary B. Bronner, Judson R. Holt, Gregory G. Freeman, Matthias Schaller, R. Murphy, J. Pellerin, J. Klais, Kai Frohberg, A. Neu, N. Kepler, R. Bolam, C. Labelle, Anuj Madan, K. Hempel, C. Reichel, Heike Salz, J. Hontschel, T. Sato, J. Cheng, D. Greenlaw, Linda Black, Paul D. Agnello, K. Ida
Publikováno v:
Scopus-Elsevier
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a n
Autor:
G. Burbach, A. Antreasyan, P. Tran, S. Subbanna, Anupama Mallikarjunan, R. Malik, Manfred Horstmann, A. Wei, G.B. Bronner, William F. Clark, S.-P. Sun, C.W. Lai, R. van Bentum, Dureseti Chidambarrao, S. Allen, H.S. Yang, Michael P. Belyansky, J. Buller, H. Kuroda, B. Tessier, Matthias Schaller, E. Ehrichs, J. Sudijono, Anthony I. Chou, Siddarth A. Krishnan, Bernard A. Engel, H.K. Lee, Y. Kohyama, Richard Wise, R. Wong, F.F. Jamin, Michael Raab, C. Wann, X. Chen, P. Huebler, Yujun Li, H.Y. Ng, Victor Chan, J. Klais, K. Bandy, W. Lai, W.-H. Lee, Kartik Subramanian, H. Harifuchi, Siddhartha Panda, L.T. Su, Th. Feudel, Hartmut Ruelke, S.W. Crowder, K. Wieczorek, S.F. Huang, E.H. Lim, G. Grasshoff, Shreesh Narasimha, Jörg Hohage, Markus Lenski, I.Y. Yang, Zhihong Chen, A. McKnight, Rolf Stephan, G. Sudo, Martin Gerhardt, Scott Luning, C. Schwan, S. Goad, K. Matsumoto, J. Nayak, Rajesh Rengarajan, N. Kepler, Kai Frohberg, M. Steigerwalt, Heike Salz, J.C. Arnold, D. Greenlaw, Rama Divakaruni, A. Bonnoit, R. Jagannathan, Paul D. Agnello, Yoshiaki Toyoshima
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 1
Autor:
A. Hellmich, S. Weiher-Telford, C. Ziemer-Popp, Th. Feudel, H.-J. Engelmann, Guido Koerner, A. Wei, Rolf Stephan, O. Herzog, K. Hempel, Jens-Peter Biethan, C. Reichel, J. Hontschel, Helmut Bierstedt, Peter Javorka, A. Neu, J. Klais, E. Sanchez, T. Mantei, M. Horstmann, D. Greenlaw, O. Luckner, P.-O. Hansson, N. Kepler, Michael Raab, Markus Lenski, Bernhard Trui, A. Samoilov, Christoph Schwan, Ralf Otterbach, Thorsten Kammler, Gert Burbach
Publikováno v:
Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials.
Autor:
Guido Koerner, Hans-Jürgen Engelmann, H. Nii, Martin Gerhardt, Andy Wei, Hartmut Ruelke, L. T. Su, Mukesh Khare, Manfred Horstmann, Rolf Stephan, O. Herzog, Ralf Otterbach, Judson R. Holt, Dureseti Chidambarrao, Peter Javorka, Helmut Bierstedt, C. Reichel, P. Hubler, Heike Salz, J. Hontschel, H. Chen, Thorsten Kammler, Dominic J. Schepis, A. Hellmich, T. Sato, Woo-Hyeong Lee, N. Kepler, S. Liming, David M. Fried, Matthias Schaller, Michael Raab, Thomas Feudel, D. Greenlaw, Shih-Fen Huang, John Pellerin, Kai Frohberg, A. Neu, Patrick Press, J. Klais, Siddhartha Panda, Andrew Waite, K. Hempel, Markus Lenski, Bernhard Trui, Jörg Hohage, K. Rim, M. Trentsch
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization pro
Autor:
D. Greenlaw, Rolf Stephan, James F. Buller, Jon D. Cheek, Michael Raab, Christoph Schwan, Markus Lenski, N. Kepler, Karsten Wieczorek, Martin Gerhardt, Gert Burbach, Thomas Feudel, Jörg Hohage, Kai Frohberg, Andy Wei, J. Klais, S. Krishnan, Scott Luning, Peter Huebler, Matthias Schaller, Manfred Horstmann, G. Grasshoff, R. van Bentum, Hartmut Ruelke
Publikováno v:
2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SO
Autor:
J. Klais, H. J. Möller, Bruno K. Meyer, A. Polity, Reinhard Krause-Rehberg, Torsten E.M. Staab, Martti J. Puska
CuInSe2 was studied in the as-grown state and after low-temperature (4 K) 2 MeV electron irradiation. The positron bulk lifetime of 235 ps was measured for the unirradiated sample. The positron bulk lifetime was theoretically calculated and is in goo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::560f1a5cc0d96048c1976d3a92a01cdc
https://aaltodoc.aalto.fi/handle/123456789/17873
https://aaltodoc.aalto.fi/handle/123456789/17873
Autor:
Manfred Horstmann, David Greenlaw, P. Huebler, R. Stephan, Th. Feudel, A. Wei, K. Frohberg, M. Lenski, K. Wieczorek, G. Burbach, C. Schwan, P. Press, Th. Kammler, H. Bierstedt, R. Otterbach, A. Neu, M. Schaller, H. Salz, J. Hohage, H. Ruelke, J. Klais, G. Grasshoff, E. Ehrichs, S. Goad, M. Raab, N. Kepler
Publikováno v:
ECS Meeting Abstracts. :535-535
not Available.