Výsledky vyhledávání - "J. Innocenti"

TCAD investigation of zero-cost high voltage transistor architectures for logic memory circuits

Autor: K. Coulié, Jordan Locati, Stephan Niel, Vincenzo Della Marca, Olivier Paulet, Julien Delalleau, J. Innocenti, Arnaud Regnier, Christian Rivero

Publikováno v: 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2019, Udine, Italy. pp.1-4, ⟨10.1109/SISPAD.2019.8870384⟩

International audience; In this paper, a new device architecture has been studied by TCAD process simulations in order to provide the improvements on the electrical characteristics. We focus mainly on the drain-bulk junction breakdown voltage, of a d

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::49310d915e8db6f39455c6c174b89a5f
https://hal.archives-ouvertes.fr/hal-02332336

Zobrazit plný text záznamu

All regimes mobility extraction using split C–V technique enhanced with charge-sheet model

Autor: François H. Julien, Q. Hubert, B. Rebuffat, L. Masoero, M. Carmona, J. Innocenti, P. Chiquet, Pascal Masson, L. Lopez

Publikováno v: Solid-State Electronics. 111:52-57

In this paper, carrier effective mobility is accurately extracted from weak to strong inversion and from ohmic to saturation regimes by pairing the split C – V technique with charge-sheet model. In weak inversion, both electron and hole effective m

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1ab7b54224f778d00e7fe57a2f4d4039
https://doi.org/10.1016/j.sse.2015.05.001

Zobrazit plný text záznamu

Dynamic current reduction of CMOS digital circuits through design and process optimization

Autor: L. Lopez, J. Castellan, L. Welter, François H. Julien, N. Borrel, Stephan Niel, J. Innocenti, J-M. Portal, Philippe Dreux, Pascal Masson, Jacques Sonzogni

Publikováno v: PATMOS

This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::08ebb55476322b94e37ed786b96ccece
https://doi.org/10.1109/patmos.2015.7347590

Zobrazit plný text záznamu

NMOS drive current enhancement by reducing mechanical stress induced by Shallow Trench Isolation

Autor: G. Bouton, François H. Julien, Stephan Niel, Q. Hubert, J. Innocenti, Pascal Fornara, A. Regmer, J.-M. Portal, C. Rivero, L. Lopez, Pascal Masson

Publikováno v: 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

This paper presents a new solution to reduce the mechanical stress impact of Shallow Trench Isolation (STI) by adding polysilicon in STI and thus, improve MOSFET performances. Indeed, when a polysilicon wall is used, the drive current of NMOS transis

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2a514a92f4a75c56f04d51db314ba352
https://doi.org/10.1109/edssc.2015.7285134

Zobrazit plný text záznamu

Layout optimizations to decrease internal power and area in digital CMOS standard cells

Autor: Stephan Niel, Pascal Masson, Q. Hubert, Jacques Sonzogni, Arnaud Regnier, Franck Julien, J-M. Portal, L. Lopez, J. Innocenti

Publikováno v: MIPRO

This paper presents several layout optimizations in order to decrease both, the internal power and the area of digital standard cells. A new D flip-flop (Dff) is designed using advanced design rules and lower active widths. Post-layout simulations ar

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::217f84f9c443d0c330239daa7a028195
https://doi.org/10.1109/mipro.2015.7160523

Zobrazit plný text záznamu

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology

Autor: Franck Julien, Pascal Masson, Jean-Michel Portal, Arnaud Regnier, L. Lopez, Eric Denis, Jacques Sonzogni, Loic Welter, J. Innocenti, Emmanuel Paire, Stephan Niel, Karen Labory

Publikováno v: MWSCAS

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::29bff9a562ae5b31cbe3d17012133c09
https://doi.org/10.1109/mwscas.2014.6908560

Zobrazit plný text záznamu

Accurate multiplexed test structure for threshold voltage matching evaluation

Autor: Jean-Michel Portal, J. Innocenti, Loic Welter, Hassen Aziza, Philippe Dreux

Publikováno v: DTIS

This paper presents a multiplexed test structure able to measure a large number of transistor threshold voltages within a scribe line. To achieve this, switches are used to select a single transistor among others in a small multiplexed array. A study

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9bb247480a593d48785a1436aaccb3c8
https://doi.org/10.1109/dtis.2014.6850657

Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání