Zobrazeno 1 - 10
of 59
pro vyhledávání: '"J. Hilgenstock"'
Publikováno v:
IEEE Design & Test of Computers. 19:6-17
This 16.89 cm/sup 2/ multiprocessor system performs coding of high-resolution video streams in real time. Redundancy and self-reconfiguration techniques ensure high reliability with a suitable yield. We used our own built-in self-test approach, which
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::904d3a8ab285f63bcd7796bf0e243029
https://doi.org/10.1109/54.980049
https://doi.org/10.1109/54.980049
Publikováno v:
Great Lakes Symposium on VLSI
A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and ma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27e19c36af3feda298fcc096e3fb8518
https://doi.org/10.1109/glsv.1999.757373
https://doi.org/10.1109/glsv.1999.757373
Publikováno v:
ICECS
A development system for investigations on video signal processing in multimedia applications has been developed. This system is based on the single chip multiprocessor array MAXPE9 which integrates 9 programmable video signal processing elements AxP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::812fc592922363b0c062f5239c21af22
https://doi.org/10.1109/icecs.1996.584626
https://doi.org/10.1109/icecs.1996.584626
Publikováno v:
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon.
The architecture and implementation of a programmable processing element dedicated as building block for a large area integrated multiprocessor system is presented. The processor element allows an efficient implementation of video coding standards. I
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35e4ec4dfb01cdb7ccf45a11e1f18acf
https://doi.org/10.1109/iciss.1996.552416
https://doi.org/10.1109/iciss.1996.552416
Publikováno v:
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).
A video coding subsystem for monolithic integration in a 0.25 /spl mu/m CMOS technology has been developed. It consists of a programmable video signal processor core, up to 8 Mbit frame memory as embedded DRAM and video interfaces. The functionality
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0915dab2b402d44360b143ae232e1851
https://doi.org/10.1109/asic.1998.723023
https://doi.org/10.1109/asic.1998.723023
Publikováno v:
1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon.
The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::42d34ee6513cff42bedffececc491023
https://doi.org/10.1109/iciss.1997.630270
https://doi.org/10.1109/iciss.1997.630270
Publikováno v:
DFT
An architecture of a multiprocessor coding system suitable for large area integration has been developed. Application field is video coding according to the international standards ISO MPEG-2 and ITU-T H.263 or similar methods. It is based on process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2be53e8764f1a98c0823252669054239
https://doi.org/10.1109/dftvs.2000.887148
https://doi.org/10.1109/dftvs.2000.887148
Publikováno v:
2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).
A programmable single-chip multiprocessor system for video signal processing applications has been developed. It integrates four processing nodes with on-chip DRAM and application-specific interfaces. The embedded DRAM is primarily used as a frame bu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe6c6c3ad6d4758cd726e9760920e8e6
https://doi.org/10.1109/sips.2000.886700
https://doi.org/10.1109/sips.2000.886700
Publikováno v:
DAC
The video signal processor AxPe1280V has been developed for implementation of different video coding applications according to standards like ITU-T H.261/H.263, and ISO MPEG-1I2. It consists of a RISC processor supplemented by a coprocessor for convo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d90a5468dd6055f42c3a4c52cce00c3
https://doi.org/10.1145/277044.277054
https://doi.org/10.1145/277044.277054
Publikováno v:
International Journal of Control, Automation & Systems; Mar2024, Vol. 22 Issue 3, p963-975, 13p