Výsledky vyhledávání

New generation of reactive pre-clean prior to barrier–seed deposition to preserve ULK integrity

Autor: M. Delavant, Denis Guiheux, S. Guggilla, T. H. Ha, J. Guillan, D. Galpin, Marc Juhel, S. Hong, John C. Forster, P. Jian, Sonarith Chhun, B. Bozon

Publikováno v: Microelectronic Engineering. 92:38-41

Advanced interconnects development requires introduction of porous ultra low k (ULK) dielectrics enhancing product performance through parasitic capacitance reduction. ULK layers are characterized by higher carbon content and lower mechanical propert

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f8641d07ab4d3cfda43a4d8300a50527
https://doi.org/10.1016/j.mee.2011.05.038

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New generation of Self Ionized Plasma copper seed for sub 40nm nodes

Autor: M. C. Luche, J. Guillan, Sonarith Chhun, P. Normandon, E. Petitprez, Lucile Arnaud, K. Haxaire, E. Richard, C. Monget, D. Galpin

Publikováno v: Microelectronic Engineering. 88:697-700

Two seed deposition hardware are compared in this paper: a standard Self Ionized Plasma (SIP) standard chamber and a new generation chamber allowing Cu deposition and re-sputtering simultaneously. TEM characterizations exhibits better features covera

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::401122ea0f103eb2d28de83c4e50ef30
https://doi.org/10.1016/j.mee.2010.07.035

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32nm node BEOL integration with an extreme low-k porous SiOCH dielectric k=2.3

Publikováno v: Microelectronic Engineering. 87:316-320

A 32nm node BEOL integration scheme is presented with 100nm metal pitch at local and intermediate levels and 50nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32nm RC performance specifications, extreme low-k (ELK) porous SiOCH k

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8e61fa6273f887f806348d3683ae5ac2
https://doi.org/10.1016/j.mee.2009.07.008

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Hybrid punch through approach to address electroless related integration issues of hybrid CoWP/SiCN barriers

Autor: J. Guillan, Joaquim Torres, V. Girault, R. Gras, M. Hauschildt, E. Petitprez, P. Brun, M. Gall, E. Ollier, R. Delsol, L.G. Gosset

Publikováno v: Microelectronic Engineering. 84:2629-2633

Integration of CoWP self-aligned barriers in hybrid stack with SiCN liner in a standard 65nm technology node integration scheme faces several issues. For example, bowing of upper metal level occurs due to the interaction between CoWP and etch plasma

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b6dbb18cfd4be80f99aa184cc7bc2c93
https://doi.org/10.1016/j.mee.2007.05.019

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Cu surface treatment influence on Si adsorption properties of CuSiN self-aligned barriers for sub-65nm technology node

Autor: J.C. Dupuy, G. Bryce, Nicolas Gaillard, S. Chhun, J. Vitiello, V. Girault, M. Hopstaken, J. Guillan, Joaquim Torres, L.G. Gosset, B. Van Schravendijk, J. Michelon, Pascal Bancken, S. Courtas, R. Gras, Marc Juhel, L. Pinzelli, C. Debauche

Publikováno v: Microelectronic Engineering. 83:2094-2100

Self-aligned barriers are widely investigated either in replacement of dielectric liners to decrease the total interconnect k value or as a treatment prior standard dielectric barrier deposition to improve reliability performances. In this paper, a t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a69f8a8c59131b6a249c8aad8379dfdd
https://doi.org/10.1016/j.mee.2006.09.013

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Characterization and impact of reduced copper plating overburden on 45 nm interconnect performances

Autor: P. Vannier, Ph. Normandon, E. Petitprez, V. Caubet-Hilloutou, J. Guillan, K. Haxaire, D. Bellet, M. Mellier, P. Caubet, O. Dubreuil

Publikováno v: Microelectronic Engineering
Microelectronic Engineering, Elsevier, 2010, 87 (3), pp.421-425. ⟨10.1016/j.mee.2009.07.002⟩
Microelectronic Engineering, 2010, 87 (3), pp.421-425. ⟨10.1016/j.mee.2009.07.002⟩

During first metal level interconnects fabrication, a controlled modification of the electro-deposited copper over-deposition (overburden) is performed using a partial chemical-mechanical polishing (CMP) step. Next, copper microstructure is stabilize

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cebdc7518e6855fef2093e47d1a5a42e
https://hal.archives-ouvertes.fr/hal-01067591

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In situ post etching treatment as a solution to improve defect density for porous low-k integration using metallic hard masks

Autor: Vincent Arnal, D. Roy, Thierry Chevolleau, C. Verove, J. Guillan, Nicolas Posseme, L. Arnaud, M. Guillermet, J. Ramard, E. Richard, S. Chhun, D. Galpin, R. Bouyssou, C. Monget, Olivier Joubert, Thibaut David

Publikováno v: 2009 IEEE International Interconnect Technology Conference.

H 2 , O 2 , NH 3 and CH 4 in situ post-etching treatments (PET) have been investigated as a solution to prevent the residues formation (TiFx based) on TiN metallic hard mask (MHM) after etching in fluorocarbon based plasmas. The PET impact on the res

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e5c428651773c0d2332b1b4225a0e87a
https://doi.org/10.1109/iitc.2009.5090398

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Demonstration of TFHM scalability to 32 nm node BEOL interconnect and extendibility to ELK k ≤ 2.3 dielectric material

Publikováno v: 2009 IEEE International Interconnect Technology Conference.

A 32 nm node BEOL demonstrator using Trench First Hard Mask (TFHM) architecture is realized. The dual damascene process is performed with ELK dielectric at line and via level and with an adapted metallization in order to meet ITRS specifications. ELK

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::713e7a42b5208b35772e44a54a9caec1
https://doi.org/10.1109/iitc.2009.5090370

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