Zobrazeno 1 - 10
of 46
pro vyhledávání: '"J. Gregory Steffan"'
Autor:
Jeffrey Kingyens, J. Gregory Steffan
Publikováno v:
International Journal of Reconfigurable Computing, Vol 2011 (2011)
We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation. In particular, our soft processor archit
Externí odkaz:
https://doaj.org/article/7e44838572084841b397791a872d1d29
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 10:1-23
By using resource sharing field-programmable gate array (FPGA) compute engines, we can reduce the performance gap between soft scalar CPUs and resource-intensive custom datapath designs. This article demonstrates that Thread- and Instruction-Level pa
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 7:1-23
Multi-ported memories are challenging to implement on FPGAs since the block RAMs included in the fabric typically have only two ports. Hence we must construct memories requiring more than two ports, either out of logic elements or by combining multip
Publikováno v:
IEEE Transactions on Computers. 63:664-678
The increased demand for on-chip communication bandwidth as a result of the multicore trend has made packet-switched networks-on-chip (NoCs) a more compelling choice for the communication backbone in next-generation systems . However, NoC designs hav
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 4:1-14
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchronization in a way that is scalable and easy to program becomes a challen
Publikováno v:
ACM Transactions on Architecture and Code Optimization. 5:1-33
Thread-level speculation (TLS) allows us to automatically parallelize general-purpose programs by supporting parallel execution of threads that might not actually be independent. In this article, we focus on one important limitation of program perfor
Publikováno v:
ACM Transactions on Computer Systems. 26:1-50
With the advent of chip multiprocessors, exploiting intratransaction parallelism in database systems is an attractive way of improving transaction performance. However, exploiting intratransaction parallelism is difficult for two reasons: first, sign
Publikováno v:
ACM SIGARCH Computer Architecture News. 35:9-19
Embedded systems designers that use FPGAs are increasingly including soft processors in their designs (configurable processors built in the programmable logic of the FPGA). While there has been a significant amount of research on adding custom instru
Autor:
Jeff Da Silva, J. Gregory Steffan
Publikováno v:
ASPLOS
Pointer analysis is a critical compiler analysis used to disambiguate the indirect memory references that result from the use of pointers and pointer-based data structures. A conventional pointer analysis deduces for every pair of pointers, at any pr
Publikováno v:
FPT
Implementing systems on FPGA soft-processors, rather than as custom hardware, eases and accelerates the development process, but at the cost of a great reduction in performance. Orthogonal to limitations in parallelism or clock frequency, this reduct