Zobrazeno 1 - 5
of 5
pro vyhledávání: '"J. Greg Massey"'
Publikováno v:
2021 IEEE Microelectronics Design & Test Symposium (MDTS).
Many IC thermal simulations use only a small volume due to machine/EDA tool constraints. This work presents a thermal TCAD simulation methodology on a large-scale 7nm circuit using available thermal TCAD tools. The circuit model is based on a 3 x 3 a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c29e5bc85fe323f86c4a9925dcc98af2
https://doi.org/10.1109/mdts52103.2021.9476141
https://doi.org/10.1109/mdts52103.2021.9476141
Autor:
Nilufa Rahim, Stew Rauch, Yanfeng Wang, Fen Chen, J. Greg Massey, Joe Lukaitis, Michael J. Hauser, Ernest Y. Wu, Paul A. Hyde, Steve Mittl, Sudesh Saroop, Ann Swift, Dimitris P. Ioannou
Publikováno v:
2012 IEEE International Reliability Physics Symposium (IRPS).
The reliability characterization of a high performance 32nm SOI CMOS technology featuring gate first High-K Metal Gate and embedded High-K Metal Fill DRAM is presented. This technology features high performance 0.9V thin dielectric devices and 1.5V t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c962cf915233f69ff5d7fb4631f03a7
https://doi.org/10.1109/irps.2012.6241866
https://doi.org/10.1109/irps.2012.6241866
Autor:
Kai Zhao, D. Badami, Eduard A. Cartier, Rahul M. Rao, R. Bolam, K. Das, Dimitris P. Ioannou, Aditya Bansal, Barry Linder, John M. Aitken, J. Greg Massey, Steven W. Mittl, G. La Rosa, Jae-Joon Kim, Michael J. Hauser, James H. Stathis
Publikováno v:
2011 International Reliability Physics Symposium.
A robust reliability characterization / modeling approach for accurately predicting Bias Temperature Instability (BTI) induced circuit performance degradation in High-k Metal Gate (HKMG) CMOS is presented. A series of device level stress experiments
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8dd598f27d2de69ae9facf7695b8f98c
https://doi.org/10.1109/irps.2011.5784559
https://doi.org/10.1109/irps.2011.5784559
Autor:
G. Braceras, M. Khare, D. Turner, Baozhen Li, Ernest Y. Wu, J. Greg Massey, Jordi Suñé, Ann Swift, S. Tous, M. Johnson, R. Bolam
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
Based on fundamental understanding of oxide breakdown (BD) physics established for thin oxides, we demonstrate that product circuit malfunction such as SRAM V min failure due to intrinsic TDDB can be accurately predicted. This prediction is based on
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::416312cd4cf42e023edddea3b83a5ba8
https://doi.org/10.1109/iedm.2009.5424340
https://doi.org/10.1109/iedm.2009.5424340
Autor:
I. Yang, F. Zhang, A. Tilke, P. Wrschka, Y.-H. Lin, J. Lian, P. Nguyen, V. Ramanchandran, Gregory M. Johnson, L.S. Leong, Atul C. Ajmera, A. Ebert, S.O. Kim, H. Zhuang, M.-C. Sun, J.-P. Kim, Andy Cowley, Christopher V. Baiocco, J.-H. Ku, W. Lin, J. Greg Massey, Alvin G. Thomas, M. Naujok, A. Vayshenker, G. Leake, A. Fischer, M. Sherony, E. Kaltalioglu, K. Hooper, Dirk Vietzke, C. Griffin, Y.-W. Teh, W. Gao, J. Sudijohno, Manfred Eller, Randy W. Mann, G. Matusiewicz, Y.K. Siew, T. Schiml, Renee T. Mo, S.-M. Choi, R. Knoefler, W.L. Tan, J. Benedict, T. Pompl, J.-H. Yang, F.F. Jamin, Fernando Guarin, K.C. Park, K.-W. Lee, An L. Steegen, Jae-Eun Park, S. Scheer, V. Klee, D.H. Hong, L. Tai, V. Ku, S.L. Liew
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80b515e6807384d732a1a136ebc7ef9d
https://doi.org/10.1109/iedm.2005.1609267
https://doi.org/10.1109/iedm.2005.1609267