Zobrazeno 1 - 10
of 117
pro vyhledávání: '"J. Gaisler"'
Publikováno v:
Plant, Soil and Environment, Vol 50, Iss 7, Pp 324-331 (2004)
The effect of different cutting and mulching regimes on the structure of the sward and plant species diversity of semi-natural meadow (Arrhenatherion alliance) was investigated in manipulative experiment over five years. Mulching once a year in Septe
Externí odkaz:
https://doaj.org/article/ce04533d2d484476a227ae08bd69b98d
Publikováno v:
2011 12th European Conference on Radiation and Its Effects on Components and Systems.
GR712RC is a dual core 32-bit fault-tolerant SPARC™V8/LEON3-FT processor that has been developed and manufactured by Ramon Chip Ltd and AeroflexGaisler AB and characterized for radiation effects. It is designed with AeroflexGaisler's intellectual p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f78725fd61a95f2e994b3e0f6799104
https://doi.org/10.1109/radecs.2011.6131334
https://doi.org/10.1109/radecs.2011.6131334
Akademický článek
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Publikováno v:
2009 IEEE Radiation Effects Data Workshop.
Special SEU test software is used to monitor the single-bit per word corrected errors in the internal SRAM of the LEON 3 fault tolerant processor. SEL and TID results are discussed.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b07cefcb833291712e7ec45da0315c4d
https://doi.org/10.1109/redw.2009.5336299
https://doi.org/10.1109/redw.2009.5336299
Publikováno v:
FPL
This paper presents a DVS (Dynamic Voltage Scaling) enabled SoC (System-on-Chip) processing platform based on the Leon3 open-source processor and dynamically reconfigurable clock synthesis technology available in Virtex-4 Xilinx FPGAs. A special DVS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1bef211db2cd947912503de174ac044f
https://doi.org/10.1109/fpl.2007.4380689
https://doi.org/10.1109/fpl.2007.4380689
Publikováno v:
DDECS
The paper presents a case study on the implementation of LEON-2 processor system on a chip. LEON-2 core is used as a general purpose processor for the concept of high-performance low-power wireless engine. The implemented processor system has been ve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a0ff1bdd8821e61cd17a8e0e2e433a6
https://doi.org/10.1109/ddecs.2006.1649569
https://doi.org/10.1109/ddecs.2006.1649569
Akademický článek
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Autor:
J. Gaisler
Publikováno v:
10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings..
Summary form only given. We believe that one significant reason for the high cost and poor performance of space-based computers is the lack of standardization. While it can be argued that the proprietary architectures of space computers are results o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a94cf1d915e5c5cb9c5b7361f69cb51
https://doi.org/10.1109/prdc.2004.1276586
https://doi.org/10.1109/prdc.2004.1276586
Autor:
J. Gaisler
Publikováno v:
DSN
The architecture and implementation of the LEON-FT processor is presented. LEON-FT is a fault-tolerant 32 bit processor based on the SPARC V8 instruction set. The processors tolerates transient SEU errors by using techniques such as TMR registers, on
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b530a851e343d9a3eb69e3bba231af5
https://doi.org/10.1109/dsn.2002.1028926
https://doi.org/10.1109/dsn.2002.1028926
Autor:
J. Gaisler
Publikováno v:
FTCS
This paper describes the concurrent error-detection methods employed in the ERC32, a 32-bit processing core for embedded space flight applications. The processor core consists of three devices; an integer unit, a floating point unit and a memory cont
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eece7a6bb14436adb3f24cf7efb85f0e
https://doi.org/10.1109/ftcs.1994.315650
https://doi.org/10.1109/ftcs.1994.315650