Zobrazeno 1 - 10
of 65
pro vyhledávání: '"J. Dechamp"'
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Autor:
Simon Deleonibus, C. Lecouvey, J. Dechamp, Jean-Paul Mazellier, O. Faynot, M. Rabarot, Francois Andrieu, Samuel Saada, J.-C. Roussin, J.P. Roger, Philippe Bergonzo, Laurent Clavelier, Julie Widiez
Publikováno v:
Diamond and Related Materials. 19:796-805
In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using either Smart Cut™ or bonded and Etched-Back Silicon On Insulator (BESOI) technology. Thanks to the development of an innovative smoothening process, polycrystalline
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eea7f4929537c83e5eca81355df48f3a
https://doi.org/10.1016/j.diamond.2010.01.049
https://doi.org/10.1016/j.diamond.2010.01.049
Autor:
Francois Andrieu, Samuel Saada, Laurent Clavelier, Marc Rabarot, Vincent Delaye, J.-C. Roussin, Simon Deleonibus, O. Faynot, J. Dechamp, Jean-Paul Mazellier, P. Bergonzo, Julie Widiez
Publikováno v:
Solid-State Electronics. 54:158-163
In this paper, Silicon on Diamond (SOD) substrates were fabricated using the direct bonding process in two different technologies: the BESOI (Bonded and Etched-back SOI) and the Smart-Cut™ process. The polycrystalline diamond (C∗) film deposited
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76fb0f033ff59780f11a9e2a493266e4
https://doi.org/10.1016/j.sse.2009.12.012
https://doi.org/10.1016/j.sse.2009.12.012
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Autor:
Severine Cheramy, L. Gabette, Nacima Allouti, L. Vignoud, E. Rolland, N. Sillon, P. Montmeat, A. Jouve, K. Vial, Christophe Aumont, V. Loup, T. Magis, Perceval Coudrain, C. Laviron, F. Foumel, R. Kachtouli, T. Mourier, R. Eleouet, Maxime Argoud, C. Ratin, R. Hida, J. Dechamp, L. Bally, M. Pellat
Publikováno v:
2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).
The purpose of this paper is to investigate integration results of 300mm silicon wafers thinned at 80μm down to 50μm using the innovative temporary ZoneBOND™ technology to handle the device during the process flow. A focus on the coating/bonding
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f6c3735660cb3c65dd0a89cf2d1d23a
https://doi.org/10.1109/eptc.2012.6507125
https://doi.org/10.1109/eptc.2012.6507125
Autor:
Masataka Hasegawa, Philippe Bergonzo, Julie Widiez, Sorin Cristoloveanu, K. Tsugawa, L. Brevard, Mathieu Lions, M. Rabarot, J. Dechamp, Jean-Paul Mazellier, Francois Andrieu, Samuel Saada, O. Faynot, Simon Deleonibus, V. Delaye, Laurent Clavelier
Publikováno v:
2009 IEEE International SOI Conference.
We have fabricated Silicon-On-Diamond (SOD) substrates on which, for the first time, we integrated n and p Fully Depleted MOSFETs high-K/metal gate down to 200nm gate length. The devices show excellent electrical characteristics and a 57% improvement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5db41e9008479295ff9de1091b1027ad
https://doi.org/10.1109/soi.2009.5318735
https://doi.org/10.1109/soi.2009.5318735
Autor:
J. Dechamp, Laurent Clavelier, Virginie Loup, C. Richtarch, J.M. Hartmann, N. Kernevez, Carlos Mazure, Fabrice Letertre, C. Morales, H. Moriceau, G. Raskin, A. Beaumont, F. Chieux, Chrystel Deguet, Frederic Allibert, A.M. Charvet
Publikováno v:
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
This paper discusses on the development of germanium-on-insulator (GeOI) structures made by using the smart cut technology, in the preparation of the donor wafer and on the Ge epi development. Thin single crystal layers of Ge [001] have been successf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::510a99444623418415d55502d3559776
https://doi.org/10.1109/soi.2004.1391571
https://doi.org/10.1109/soi.2004.1391571
Autor:
J. Dechamp, A.M. Charvet, C. Gorla, Fabrice Letertre, B. Aspar, C. Morales, Carlos Mazure, B. Ghyselen, Christelle Lagahe-Blanchard, C. Yalicheff, N. Kernevez, M. Zussy, H. Moriceau
Publikováno v:
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
To illustrate the challenges and potential of advanced wafer bonding, this paper deals with the boding of silicon wafers, which are patterned and partially oxidized. Two kinds of bonded structures are reported. The buried oxide is patterned in thick
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41ec2af4370785ffa3b4d1991657afe0
https://doi.org/10.1109/soi.2004.1391617
https://doi.org/10.1109/soi.2004.1391617
