Zobrazeno 1 - 10
of 16
pro vyhledávání: '"J. Anidjar"'
Autor:
K.R. Lakshmikumar, J. Anidjar
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:111-115
This paper describes a CMOS line driver that operates from a 3 V power supply and delivers a peak current of about 100 mA to the load. The novel features of the circuit are high power efficiency, an output pulse shape and amplitude independent of pow
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::456c07b4973d318fa51e083b3dcd6bc3
https://doi.org/10.1109/4.736664
https://doi.org/10.1109/4.736664
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:312-320
A parallel-pipelined A/D converter with an area and power efficient architecture is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-b pipeline is realized using just three am
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89fd39dc01d69f90082ee0903f096dcd
https://doi.org/10.1109/4.557628
https://doi.org/10.1109/4.557628
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1723-1729
A line driver with a high-swing output stage is reported. The prototype, in a 0.9- mu m CMOS technology, is capable of delivering 9 V/sub pp-diff/ with 80 dB linearity operating from a single 9 V/sub pp-diff/ 5 V supply. The nearly rail-to-rail volta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::77036a8439efaaeaef40063140da2e81
https://doi.org/10.1109/4.173098
https://doi.org/10.1109/4.173098
Autor:
O.E. Agazzi, C.M. Gerveshi, M.L. Heiskanen, R.B. Blake, T.R. Peterson, P.H. Tracy, M.R. Dwarakanath, R.F. Shaw, W.R. McDonald, V. Friedman, R.W. Walden, J. Kumar, D.L. Price, G.A. Wilson, J. Anidjar, H. Khorramabadi, N.L. Gottfried, J.M. Khoury, Nallepilli S. Ramesh
Publikováno v:
Proceedings of the IEEE Custom Integrated Circuits Conference.
Architectural and circuit innovations resulting in a 260mW single-chip ISDN U-interface transceiver wii h a range of more than 21Kft of AWG26 cable are described. These include a new scheme for jitter compensation using a two-phase decimator that res
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::122cfaad70299a65ad50170bf466c34e
https://doi.org/10.1109/cicc.1992.591870
https://doi.org/10.1109/cicc.1992.591870
Autor:
K. Nagaraj, Stephen H. Lewis, R.G. Renninger, R.S. Shariatdoust, J. Alsayegh, J. Anidjar, H.S. Fetterman
Publikováno v:
Proceedings of Custom Integrated Circuits Conference.
An efficient architecture for a pipelined A/D converter is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-bit converter is realized using just 3 amplifiers (instead of 7 amp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ec4df3335b7097a19b9ccc7e47f57f1b
https://doi.org/10.1109/cicc.1996.510589
https://doi.org/10.1109/cicc.1996.510589
Autor:
M.R. Dwarakanath, P.H. Tracy, K.M. Tham, R. Ramachandran, K.R. Lakshmikumar, A.R. Mastrocola, D.E. Sherry, J. Anidjar, G.T. Brauns, S.A. Werner
Publikováno v:
1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.
This paper describes the low-power techniques used to design the Clock/Data recovery, Jitter Filter and the high current Line Driver circuits in a Quad Line Interface for DS1/CEPT applications.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52a9b664fbd58b1e051ef5134bc6442b
https://doi.org/10.1109/lpe.1995.482458
https://doi.org/10.1109/lpe.1995.482458
Publikováno v:
1983 International Electron Devices Meeting.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50ad9231aef49ef0bd35834a70cdf99c
https://doi.org/10.1109/iedm.1983.190613
https://doi.org/10.1109/iedm.1983.190613
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