Zobrazeno 1 - 10
of 23
pro vyhledávání: '"J-C. Giraudin"'
Autor:
Roberto Gonella, Tomasz Brozek, Meindert Lunenborg, J.-C. Giraudin, Christopher Hess, B. Martinet, Franck Arnaud, Laurent Garchery, Kelvin Doong, Christian Dutto
Publikováno v:
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
FDSOI technology has been proposed as an alternative device scaling path which offers benefits of tunable, superior electrostatics transistor while maintaining simplicity of planar integration. New device type and integration elements brought up chal
Autor:
S. Desmoulins, J.-C. Giraudin, D. Fried, B. Vianne, C. Beylier, Pierre Morin, A. Juncker, Roberto Gonella
Publikováno v:
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
The ultra-thin body-bias (UTBB) and fully- depleted silicon on insulator (FDSOI) 28nm technology offers the capability of extreme low power performance, in part because of the use of ultra-thin buried oxide. This unique capability could be jeopardize
Autor:
D. Tsamados, Raphael Clerc, Laurent Montès, A. Bajolet, Philippe Delpech, J.-C. Giraudin, G. Pananakakis, N. Segura, Gerard Ghibaudo, E. Picollet
Publikováno v:
IEEE Transactions on Electron Devices. 54:742-751
This paper discusses the optimization of series resistance of nonplanar metal-insulator-metal capacitor, i.e., an original 3-D capacitor with a capacitance density of 35 nF/mm2, used in very large scale integration. A fully analytical and physically
Autor:
M. Proust, J-P. Manceau, Philippe Delpech, Raphael Clerc, A. Bajolet, Nicolas Gaillard, Gerard Ghibaudo, Sylvie Bruyere, Laurent Montès, J-C. Giraudin
Publikováno v:
Microelectronic Engineering. 83:2189-2194
When deposited by chemical vapor deposition (CVD), TiN layers must be post-treated with N"2/H"2 plasma. Metal-insulator-metal (MIM) capacitors using CVD-TiN as electrodes and Al"2O"3 as insulator are studied from both electrical and physico-chemical
Autor:
Philippe Delpech, Raphael Clerc, Gerard Ghibaudo, Sylvie Bruyere, S. Boret, J.-C. Giraudin, Laurent Montès, G. Pananakakis, E. Picollet, N. Segura, J.-P. Manceau, A. Bajolet
Publikováno v:
Solid-State Electronics. 50:1244-1251
Integrated circuits for analog and telecom applications require metal insulator metal (MIM) capacitors with not only a high capacitance value (typically 5 nF/mm 2 ), but also a low series resistance R s . The optimization of this latter parameter is
Autor:
L. Dumas, J.-C. Giraudin, A. Timma, P. Normandon, P. Caubet, B. Kaouache, Bernard Chenevier, Olivier Thomas
Publikováno v:
Microelectronic Engineering
Microelectronic Engineering, Elsevier, 2010, 87 (3), pp.361-364. ⟨10.1016/j.mee.2009.08.003⟩
Microelectronic Engineering, 2010, 87 (3), pp.361-364. ⟨10.1016/j.mee.2009.08.003⟩
Microelectronic Engineering, Elsevier, 2010, 87 (3), pp.361-364. ⟨10.1016/j.mee.2009.08.003⟩
Microelectronic Engineering, 2010, 87 (3), pp.361-364. ⟨10.1016/j.mee.2009.08.003⟩
International audience; Post Si(C)N hillocks are characterized on Cu interconnects networks. Each network is compounded by standard damascene process electroplated Cu lines with given width and local line density. AFM results show that total volume p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ce5e8c7a170e9fe5733d7ca35ef3fb09
https://hal.archives-ouvertes.fr/hal-01067740
https://hal.archives-ouvertes.fr/hal-01067740
Publikováno v:
SIRF 2009
SIRF 2009, Jan 2009, San Diego, Californie, United States
SIRF 2009, Jan 2009, San Diego, Californie, United States
This paper presents high Q and high current on-chip inductors manufactured in an innovative Radio Frequency (RF) Back End Of Line (BEOL), made of two 3 µm thick top copper levels, integrated in an Advanced Low Power 65 nm RF CMOS technology. Achieve
Publikováno v:
Microelectronics Reliability
Microelectronics Reliability, Elsevier, 2007, 47 (4-5), pp.700-703
Microelectronics Reliability, Elsevier, 2007, 47 (4-5), pp.700-703
New applications in microelectronics need the integration of high capacitance devices. One way of this development is the integration of capacitors with 3D architecture such as trench fields. The challenge is then to deposit the dielectric material i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c05d58efb90a9dd7eb2ed5075ea17073
https://hal.archives-ouvertes.fr/hal-00196393
https://hal.archives-ouvertes.fr/hal-00196393
Autor:
Franck Badets, C. Rossato, Jean-Pierre Blanc, Thierry Jagueneau, E. Chataigner, A. Bajolet, Philippe Delpech, J.-C. Giraudin
Publikováno v:
2006 Bipolar/BiCMOS Circuits and Technology Meeting.
This paper summarizes the electrical characterization of MIM capacitor realized in three-dimensional. High density of 35nF/mm2 is obtained with low leakage current. Its integration in BiCMOS technology is demonstrated and three circuits are character
Autor:
Emmanuel Defay, Jean-Pierre Blanc, Philippe Delpech, Pascal Ancey, Pierre Garrec, J.-C. Giraudin, Bernard Andre, Marc Aid, Julie Guillan, Emmanuelle Serret, Denis Pellissier, Laurent Ulmer, David Wolozan
Publikováno v:
2006 European Solid-State Device Research Conference.
This paper describes realization and characterization of SrTiO3 (STO) high K MIM capacitors above BiCMOS integrated circuit (IC). These capacitances are connected to IC and are used as coupling capacitors.