Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Jürgen T. Rickes"'
Autor:
Rainer Waser, Steve Gilbert, Cezary Pietrzyk, James W Grace, Scott R. Summerfelt, John Y. Fong, Theodore S. Moise, Hugh P. McAdams, Angela Wang, Dave Lee, Jun Amano, Ralph H. Lanham, Jürgen T. Rickes
Publikováno v:
Integrated Ferroelectrics. 48:109-118
We present a novel sense-amplifier for FeRAM that is about 2.5 times faster than the conventional sense-amplifier. In addition, it has truly independent sense and write-back capability and resolves the well-known bit-line capacitance imbalance issues
Publikováno v:
Journal of Applied Physics. 89:3420-3425
The emerging ferroelectric technology needs a reliable model for the simulation of the ferroelectric capacitors. This model would play a crucial role in designing new ferroelectric nonvolatile memories. As a main requirement, such a model must allow
Publikováno v:
Integrated Ferroelectrics. 34:1-10
A standard 1T/1C and chain-type ferroelectric memory architecture are presented. The standard memory cell consists of a transistor connected in series to a ferroelectric capacitor while the chain-type cell connects these elements in parallel. Based o
Publikováno v:
Integrated Ferroelectrics. 40:65-82
The basic architecture of ferroelectric memories (FeRAMs) is known to be very similar to that of DRAM. Consequently, many design issues for FeRAM are already known from DRAM and have been solved by applying prior DRAM solutions. However, there are al
Autor:
Theodore S. Moise, Xiao-Hong Du, Scott R. Summerfelt, Ralph H. Lanham, Jürgen T. Rickes, R. Acklin, J. Eliason, C. Pietrzyk, Hugh P. McAdams, John Y. Fong, Y. Qui, N. Qian, Anand Seshadri, S. Natarajan, Sudhir K. Madan, J. Roscher, F. Li, W.F. Kraus, D. Liu, Terence G. W. Blake
Publikováno v:
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).
A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor
Autor:
E. Zielinski, S. Kuchimanchi, James W Grace, D. V. Taylor, Lindsey H. Hall, Francis G. Celii, G. Xing, Theodore S. Moise, D. S. Lee, Mahesh Thakre, Scott R. Summerfelt, Kelly J. Taylor, Hugh P. McAdams, Martin G. Albrecht, K. R. Udayakumar, G. Stacey, Glen R. Fox, R. Bailey, Trace Hurd, M.D. Khan, Jürgen T. Rickes, J. S. Martin, Stephen R. Gilbert, J. Rodriguez, M. Yao, A. Wang, J. Fong, Ralph H. Lanham, A. R. Thomas, Jun Amano, K. Boku, C. Pietrzyk, T. Davenport, Sanjeev Aggarwal, K. Remack, B. McKee, F. Chu, S. Sun
Publikováno v:
Digest. International Electron Devices Meeting.
We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into th