Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Jörg Hohage"'
Publikováno v:
Microelectronic Engineering. 86:408-413
In highly integrated semiconductor devices the time to failure of copper interconnects strongly depends on the properties of the copper-dielectric cap interface. In this work a production capable preparation of copper-dielectric cap interfaces with a
Autor:
D. Greenlaw, Jon D. Cheek, Manfred Horstmann, Christoph Schwan, Markus Lenski, Peter Huebler, Scott Luning, R. van Bentum, N. Kepler, Matthias Schaller, James F. Buller, Hartmut Ruelke, Kai Frohberg, Gert Burbach, Rolf Stephan, J. Klais, S. Krishnan, Jörg Hohage, Andy Wei, Th. Feudel, Michael Raab, G. Grasshoff, Karsten Wieczorek, Martin Gerhardt
Publikováno v:
Materials Science and Engineering: B. :3-8
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI t
Autor:
John A. Fitzsimmons, Vincent J. McGahay, K. Malone, M. Minami, Siddhartha Panda, Manfred Horstmann, A. Wei, Helmut Bierstedt, H. Nii, A. Waite, A. Sakamoto, Michael A. Gribelyuk, M. Cullinan-Scholl, D. Harmon, A. Hellmich, M. Kiene, Patrick Press, Hartmut Ruelke, H. Zhu, H. Chen, H. Nakayama, Anthony G. Domenicucci, G. Sudo, Henry A. Nye, P. Fisher, Hans-Jürgen Engelmann, H. VanMeer, M. Newport, X. Chen, Tenko Yamashita, Cathryn Christiansen, Hasan M. Nayfeh, Dureseti Chidambarrao, Guido Koerner, Christopher D. Muzzy, S.-F. Huang, Ralf Otterbach, David M. Fried, J. Kluth, Jörg Hohage, M. Trentsch, I. Peidous, Thorsten Kammler, Mukesh Khare, Dominic J. Schepis, K. Rim, Spooner Terry A, K. Miyamoto, P.V. McLaughlin, Michael Raab, T. H. Ivers, Dan Mocuta, D.R. Davies, Jason Gill, Scott Luning, Woo-Hyeong Lee, Gary B. Bronner, Judson R. Holt, Gregory G. Freeman, Matthias Schaller, R. Murphy, J. Pellerin, J. Klais, Kai Frohberg, A. Neu, N. Kepler, R. Bolam, C. Labelle, Anuj Madan, K. Hempel, C. Reichel, Heike Salz, J. Hontschel, T. Sato, J. Cheng, D. Greenlaw, Linda Black, Paul D. Agnello, K. Ida
Publikováno v:
Scopus-Elsevier
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a n
Autor:
G. Burbach, A. Antreasyan, P. Tran, S. Subbanna, Anupama Mallikarjunan, R. Malik, Manfred Horstmann, A. Wei, G.B. Bronner, William F. Clark, S.-P. Sun, C.W. Lai, R. van Bentum, Dureseti Chidambarrao, S. Allen, H.S. Yang, Michael P. Belyansky, J. Buller, H. Kuroda, B. Tessier, Matthias Schaller, E. Ehrichs, J. Sudijono, Anthony I. Chou, Siddarth A. Krishnan, Bernard A. Engel, H.K. Lee, Y. Kohyama, Richard Wise, R. Wong, F.F. Jamin, Michael Raab, C. Wann, X. Chen, P. Huebler, Yujun Li, H.Y. Ng, Victor Chan, J. Klais, K. Bandy, W. Lai, W.-H. Lee, Kartik Subramanian, H. Harifuchi, Siddhartha Panda, L.T. Su, Th. Feudel, Hartmut Ruelke, S.W. Crowder, K. Wieczorek, S.F. Huang, E.H. Lim, G. Grasshoff, Shreesh Narasimha, Jörg Hohage, Markus Lenski, I.Y. Yang, Zhihong Chen, A. McKnight, Rolf Stephan, G. Sudo, Martin Gerhardt, Scott Luning, C. Schwan, S. Goad, K. Matsumoto, J. Nayak, Rajesh Rengarajan, N. Kepler, Kai Frohberg, M. Steigerwalt, Heike Salz, J.C. Arnold, D. Greenlaw, Rama Divakaruni, A. Bonnoit, R. Jagannathan, Paul D. Agnello, Yoshiaki Toyoshima
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 1
Autor:
Guido Koerner, Hans-Jürgen Engelmann, H. Nii, Martin Gerhardt, Andy Wei, Hartmut Ruelke, L. T. Su, Mukesh Khare, Manfred Horstmann, Rolf Stephan, O. Herzog, Ralf Otterbach, Judson R. Holt, Dureseti Chidambarrao, Peter Javorka, Helmut Bierstedt, C. Reichel, P. Hubler, Heike Salz, J. Hontschel, H. Chen, Thorsten Kammler, Dominic J. Schepis, A. Hellmich, T. Sato, Woo-Hyeong Lee, N. Kepler, S. Liming, David M. Fried, Matthias Schaller, Michael Raab, Thomas Feudel, D. Greenlaw, Shih-Fen Huang, John Pellerin, Kai Frohberg, A. Neu, Patrick Press, J. Klais, Siddhartha Panda, Andrew Waite, K. Hempel, Markus Lenski, Bernhard Trui, Jörg Hohage, K. Rim, M. Trentsch
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization pro
Autor:
D. Greenlaw, Rolf Stephan, James F. Buller, Jon D. Cheek, Michael Raab, Christoph Schwan, Markus Lenski, N. Kepler, Karsten Wieczorek, Martin Gerhardt, Gert Burbach, Thomas Feudel, Jörg Hohage, Kai Frohberg, Andy Wei, J. Klais, S. Krishnan, Scott Luning, Peter Huebler, Matthias Schaller, Manfred Horstmann, G. Grasshoff, R. van Bentum, Hartmut Ruelke
Publikováno v:
2004 International Conference on Integrated Circuit Design and Technology (IEEE Cat. No.04EX866).
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SO
Publikováno v:
13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259).
Advanced logic devices are setting new demands for backend integration. New high-end processor families like the AMD Athlon/sup TM/ and AMD's eighth generation processor (codenamed "Hammer"), require the introduction of low-k interlayer dielectric (I