Zobrazeno 1 - 10
of 76
pro vyhledávání: '"Iwao Teramoto"'
Publikováno v:
Transactions of the Institute of Systems, Control and Information Engineers. 16:439-450
The performance of the Cell Array's structure for the Dynamically Reconfigurable Cell-Array Processor (DRCAP), which we first proposed in 1997, in actual program execution is examined. In the DRCAP, the processing of c-language program sentences, suc
Publikováno v:
Applied Surface Science. :175-178
The stability of GaAs(001)-(2 × 4)β2 surface with Si adatoms is theoretically investigated using the ab initio pseudopotential method. The calculated results imply that stable lattice sites for Si adatoms strongly depend on the adatom coverage. At
Autor:
Masaru Kazumura, Hiroki Naito, Jun Ohya, Hirokazu Shimizu, Masahiro Kume, Issey Ohta, Iwao Teramoto
Publikováno v:
Solid-State Electronics. 34:1329-1333
This paper describes successful development of a high-power short-pulse i.r. laser diode, together with numerical analyses giving a clear understanding of the operation. The novel aspect of the present laser diode is that a saturable absorber is inco
Autor:
Masaaki Yuri, Iwao Teramoto, H. Nakanishi, Hirokazu Shimizu, H. Naito, M. Kume, N. Yoshikawa, M. Kazumura, H. Nagai, Ken Hamada
Publikováno v:
Journal of Applied Physics. 68:4420-4425
We have successfully attained low‐noise and high‐power operation in GaAlAs lasers by applying high reflectivity facet coating approach to nonabsorbing mirror lasers. High reflectivity coating is used to reduce feedback induced noise coming from h
Autor:
Iwao Teramoto, Takayuki Morishita
Publikováno v:
Transactions of the Institute of Systems, Control and Information Engineers. 10:41-43
Publikováno v:
SPIE Proceedings.
We have been developing a parallel processor that it is possible to reconfigure hardware according to a software. Dynamic Reconfiguration means to change a kind of and a number of processing elements and connection between processing elements at real
Publikováno v:
SPIE Proceedings.
Three kinds of basic Variable Length Decoder were implemented on Dynamically Reconfigurable Cell Array Processor. Traditional method, Leading zeros method, Generated unique address method were discussed. The number of required resources for each Deco
Publikováno v:
SPIE Proceedings.
We have been developing a parallel processor that it is possible to reconfigure to realize a general-purpose computation at very high speed. Dynamic Reconfiguration means to change a kind of and a number of processing elements and connection between
Publikováno v:
SPIE Proceedings.
We have proposed and developed the Dynamically Reconfigurable Cell-Array Processor (DRCAP) that consists of functional Cell Arrays (CAs), and buses/bus-switches that provide with connections between CAs. A software simulator of the DRCAP is construct
Publikováno v:
SPIE Proceedings.
Our processor is featured by the architecture such that the configuration can be dynamically and optimally rearranged inreal-time. We have already developed the instruction sets, the emulation and debug programs for the present processor,utilizing ci