Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Ivan Siu-Chuang Lu"'
Autor:
Venumadhav Bhagavatula, Fan Zhang, Chechun Kuo, Anirban Sarkar, Ashutosh Verma, Tienyu Chang, Xiaohua Yu, Dae-Young Yoon, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:1257-1266
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a8cd2b3e99d4f2597224e061ec1089bf
https://doi.org/10.1109/jssc.2022.3146872
https://doi.org/10.1109/jssc.2022.3146872
Autor:
Ajaypat Jain, Venumadhav Bhagavatula, Omar Elsayed, Chechun Kuo, Daeyoung Yoon, Amitoj Singh, Xiaohua Yu, Thomas Byunghak Cho, Ivan Siu-Chuang Lu, Hariharan Nagarajan, Sangwon Son
Publikováno v:
2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
This paper presents a 26/28/39GHz millimeter-wave phased-array receiver front-end (RXFE) including two parallel paths combined at the output. Each path consists of a T/R switch, a large dynamic range low noise amplifier (LNA), and an I/Q-current-shar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76871ffe6b79e5f64c28bd9f1af3c1a2
https://doi.org/10.1109/rfic51843.2021.9490463
https://doi.org/10.1109/rfic51843.2021.9490463
Autor:
Yongping Han, Yongrong Zuo, Chih-Wei Yao, Ashutosh Verma, Pei-Yuan Chiang, Wanghua Wu, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho, Kunal Godbole, Ronghua Ni
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:1254-1265
An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock. The measured f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6cadde0fbcc9502dc1b149e80cb00f45
https://doi.org/10.1109/jssc.2019.2899726
https://doi.org/10.1109/jssc.2019.2899726
Autor:
Jeiyoung Lee, Tienyu Chang, Kim Jung-Woo, Jonghwan Lee, Daeyoung Yoon, Jae Min Kim, Sang-Wook Han, Ivan Siu-Chuang Lu, Pranav Dayal, Pritesh Vora, Hyung-Gi Kim, Jongwoo Lee, Sang Won Son, Kee-Bong Song
Publikováno v:
2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
We propose an architecture for mobile RF transceivers which integrates RISC-V micro-controller unit (MCU) to control its internal function without requiring multiple chip-to-chip control messages from the modem. The proposed architecture is utilized
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c42d9d48a3dce6d0cafc1c9f9dd9db92
https://doi.org/10.1109/rfic49505.2020.9218424
https://doi.org/10.1109/rfic49505.2020.9218424
Autor:
Chih-Wei Yao, Sang Won Son, Thomas Byunghak Cho, Ashutosh Verma, Yongrong Zuo, Kunal Godbole, Ivan Siu-Chuang Lu, Yongping Han, Pei-Yuan Chiang, Ronghua Ni, Wanghua Wu
Publikováno v:
2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
We present a low jitter, DTC-based analog fractional-N PLL with novel, background DTC gain calibration and reference clock duty cycle correction for high performance applications. The PLL achieves a 75-fs rms jitter, integrated from 10 kHz to 10 MHz
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50bb1e7db04a82ec8b4c58e0c12e913c
https://doi.org/10.1109/rfic.2018.8428844
https://doi.org/10.1109/rfic.2018.8428844
Autor:
Ivan Siu-Chuang Lu, George Chien, Hsiang-Hui Chang, Sheng-Jui Huang, Chih-Chun Tang, Tzung-Han Wu, Chinq-Shiun Chiu, Lan-Chou Cho, Chi-Yao Yu, Chih-Hao Sun, Yen-Horng Chen, Wen-Chang Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:3047-3060
A quad-band GSM/GPRS/EDGE receiver, implemented in 65 nm CMOS, complies with the ETSI standard without the need of external SAW filters. By exploring the properties of passive mixers and current-mode operation from RF to baseband, the receiver can ac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8580a712f2a36acbaa27d239928009ba
https://doi.org/10.1109/jssc.2011.2166657
https://doi.org/10.1109/jssc.2011.2166657
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 54:323-327
This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The divider operates as a voltage controlled ring oscillator with the output frequency modulated by the switching of the input transmission gate. The divide
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34374af4ad8a7483caf2bca5dd18c8ba
https://doi.org/10.1109/tcsii.2006.889741
https://doi.org/10.1109/tcsii.2006.889741
Autor:
Chris Beale, Li-Shin Lai, Fahd Ben Abdeljelil, Walid Youssef Ali-Ahmad, Tze Yee Sin, Wen-Chang Lee, Christophe Beghein, David Stephen Ivory, Jhy-Rong Chen, Ivan Siu-Chuang Lu, Charles Chiu, Jon Strange, Chi-Wei Fan, Ta-Hsin Lin, Chih-Hao Sun, Hsiang-Hui Chang, Shao-Hung Lin, Dimitris Nalbantis, Hao-Tang Shih, Paul Muller, Hsin-Hua Chen, Sheng-Jui Huang
Publikováno v:
2014 IEEE Radio Frequency Integrated Circuits Symposium.
A 40 nm CMOS transceiver supports 10 bands of HSPA+ and quad-band GSM/EDGE occupying 6.2 mm 2 of a Modem SoC. The TX supports up to 11 Mb/s HSUPA with minimal analog filtering and 42dB SNR for receive levels >-60 dBm.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d01136c03d9af9fcf6b47b0943089220
https://doi.org/10.1109/rfic.2014.6851678
https://doi.org/10.1109/rfic.2014.6851678
Autor:
Chi-Yao Yu, Lan-Chou Cho, Yen-Horng Chen, George Chien, Chih-Chun Tang, Chih-Hao Eric Sun, Ivan Siu-Chuang Lu
Publikováno v:
ISSCC
Over the last decade, significant progress has been made towards increasing integration and reducing bill of material (BOM) for GSM/GPRS/EDGE cellular systems. In modern cellular phones, transmit SAW filters have been largely eliminated with innovati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a84e87897cdc630fa7c03a62ee35f717
https://doi.org/10.1109/isscc.2011.5746355
https://doi.org/10.1109/isscc.2011.5746355
Publikováno v:
VLSI Design
This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and distortion ratio (SNDR) and bit error rate (BER) were evaluated with varyi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0402a3bd147d2c547d75f999dfa2cca
https://doi.org/10.1109/vlsid.2006.32
https://doi.org/10.1109/vlsid.2006.32