Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Ivan Piatak"'
Publikováno v:
2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus).
Nowadays, MEMS technologies have been widely developed in different areas of electronics. Many MEMS-devices such as inclinometers based on high-precision accelerometers require high measurement accuracy. For instance, incorrect values in the output s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::672afe4477db6a1fa1e5ee995c5ef063
https://doi.org/10.1109/elconrus51938.2021.9396662
https://doi.org/10.1109/elconrus51938.2021.9396662
Publikováno v:
2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus).
In this paper implementation of the integrated temperature stabilization system is discussed. Highly-linear CMOS temperature sensor with a nonlinearity level below 8% in the range from -60° to +85°С is designed. Schematic, layout and main characte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a20bf50dc68471f244fc1b5b61382dfe
https://doi.org/10.1109/eiconrus.2019.8657182
https://doi.org/10.1109/eiconrus.2019.8657182
Publikováno v:
2018 IEEE International Conference on Electrical Engineering and Photonics (EExPolytech).
In this paper two implementations of the ring amplifier for the low-power ADCs are discussed. Requirements for the DC gain of the operational amplifier depend on the resolution of the ADCs are determined. Estimated power consumption and main characte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5bed203cd471638394b774cd3248ec0
https://doi.org/10.1109/eexpolytech.2018.8564368
https://doi.org/10.1109/eexpolytech.2018.8564368
Autor:
A. S. Korotkov, Ivan Piatak
Publikováno v:
Indian Journal of Science and Technology. 9:1-4
Pipelined ADCs with digital error correction and double-sampling are demand gain error of the stage calculations at given parameters of the op-amp of the stages. In contrast to known approaches to the analysis of the 1.5-bit conversion stage, results
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76da027134d34a32adef2ce199e902ee
https://doi.org/10.17485/ijst/2016/v9i2/72205
https://doi.org/10.17485/ijst/2016/v9i2/72205
Autor:
Ivan Piatak, Aleksandr V. Sidun
Publikováno v:
2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus).
In this paper techniques for reducing power consumption of the high-resolution ADC are discussed. The main requirements for DC gain and capacitor mismatch of 2.5-bit multiplying digital-to-analog converter (MDAC) are defined. Simulation results in MA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ed15ecff1837badd36650ba5505c25b3
https://doi.org/10.1109/eiconrus.2018.8317074
https://doi.org/10.1109/eiconrus.2018.8317074
Publikováno v:
2016 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW).
Design considerations for pipelined analog-to-digital converters (ADCs) are discussed. The main requirements for DC gain and unity-gain frequency, reference voltage stability and capacitor mismatch versus desired SFDR of pipelined ADCs are presented.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ddcc0cf1c1f381e5225dd5fdaf1763d
https://doi.org/10.1109/eiconrusnw.2016.7448266
https://doi.org/10.1109/eiconrusnw.2016.7448266
Autor:
Alexander Korotkov, Ivan Piatak
Publikováno v:
Indian Journal of Science and Technology. 9
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f46b443c9b5ee7c2ef3def6da24f392f
https://doi.org/10.17485/ijst/2016/v9i4/72205
https://doi.org/10.17485/ijst/2016/v9i4/72205
Publikováno v:
2015 International Siberian Conference on Control and Communications (SIBCON).
A 14-bit 50-MS/s pipelined analog-to-digital converter (ADC) is presented. Operational amplifier (op-amp) sharing technique, 1.5 bit redundant stages based on switched capacitor circuits with inverter-based comparators and digital gain error calibrat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67dde425363df7ef4a42c23e273da3f3
https://doi.org/10.1109/sibcon.2015.7147185
https://doi.org/10.1109/sibcon.2015.7147185
Publikováno v:
2015 IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conference (EIConRusNW).
In this paper the main aspects in construction of the low-power CMOS pipelined analog-to-digital converters (ADCs) are discussed. The main requirements for a 1.5 bit redundant stage of the pipeline ADC are defined. Examples of the digital and the ana
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89ae3625d5ddc13bab100faf9fecd7e6
https://doi.org/10.1109/eiconrusnw.2015.7102273
https://doi.org/10.1109/eiconrusnw.2015.7102273
Publikováno v:
EWDTS
A 6-bit pseudo-flash ADC is presented. CMOS inverters are used instead of a reference ladder of well matched resistors and comparators to reduce power consumption of the ADC. Influence of temperature and technology process variations on the inverters
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d25856f0b03ccfba37c34c51b5f133c1
https://doi.org/10.1109/ewdts.2013.6673079
https://doi.org/10.1109/ewdts.2013.6673079