Zobrazeno 1 - 8
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pro vyhledávání: '"Itaru Hida"'
Autor:
Tetsuya Asai, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Itaru Hida, Masato Motomura, Masayuki Ikebe, Tatsuya Kaneko
Publikováno v:
Nonlinear Theory and Its Applications, IEICE. 10:373-389
Although research on the inference phase of edge artificial intelligence (AI) has made considerable improvement, the required training phase remains an unsolved problem. Neural network (NN) processing has two phases: inference and training. In the tr
Publikováno v:
Nonlinear Theory and Its Applications, IEICE. 9:466-478
Publikováno v:
Nonlinear Theory and Its Applications, IEICE. 8:235-245
In this paper, we propose a Bayesian branch-prediction circuit, consisting of an instruction-feature extractor and a naive Bayes classifier (NBC), as a machine learning approach for branch prediction. A branch predictor predicts the outcome of a bran
Publikováno v:
Circuits and Systems. :134-147
In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigura
Publikováno v:
Circuits and Systems. :253-264
Demands for low-energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user programmability by integrating nonvolatile (NV) memories such as flash memories for storing their programs, the large power consump
Publikováno v:
APCCAS
In this paper, we propose a Bayesian branch-prediction circuit consisting of an instruction-feature extractor and a naive Bayes classifier (NBC). Its purpose is to replace conventional branch predictors in modern pipelined RISC microprocessors. The p
Publikováno v:
A-SSCC
Conventional processors are energy in-efficient in that they fail to utilize the fact that most of their time and energy are spent on heavily-recursively executed small code segments. A DYNaSTA accelerator, proposed and implemented, is an architectur
Publikováno v:
ReConFig
Reconfigurable processors have widely attracted attention as an approach to realize high-performance and highly energy-efficient processors that map a target program's hot path to a reconfigurable datapath. In this paper, we propose a Control-Flow Dr