Zobrazeno 1 - 10
of 146
pro vyhledávání: '"Interrupt priority level"'
Publikováno v:
IEEE Access, Vol 9, Pp 117358-117377 (2021)
With the rapid development of the power grid, the high penetration of new energy sources and the diversity of loads have further aggravated the uncertainty of “source-load”, which has brought huge challenges to the peak shaving of the power grid.
Autor:
TuanBu Wang
Publikováno v:
2020 International Conference on Virtual Reality and Intelligent Systems (ICVRIS).
The series of MCS 51 Single Chip Microcomputer (SCM) only have two external interrupts and two interrupt priorities. This paper introduces three methods for the extension of external interrupts. It also specifies the program of each extension through
Publikováno v:
IEEE Access, Vol 7, Pp 127066-127077 (2019)
Safe operation control systems are the most important aspect of medical device development apart from the machine's function itself. Due to the fact that machines are used on people, how people can protect themselves from intelligent/programmed autom
Autor:
Edward L. Lamie
ThreadX is a popular RTOS for embedded designs using the MIPS processor. ThreadX complements the MIPS processor because both are extremely simple to use and are very powerful. An exception is an asynchronous event or error condition that disrupts the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::103d3d21651f84534b82ef889cb1060e
https://doi.org/10.1201/9780429187858-6
https://doi.org/10.1201/9780429187858-6
Publikováno v:
Spink, T, Wagstaff, H & Franke, B 2016, Efficient Asynchronous Interrupt Handling in a Full-System Instruction Set Simulator . in LCTES 2016 Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems . pp. 1-10, 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, Santa Barbara, United States, 13/06/16 . https://doi.org/10.1145/2907950.2907953
LCTES
LCTES
Instruction set simulators (ISS) have many uses in embedded software and hardware development and are typically based on dynamic binary translation (DBT), where frequently executed regions of guest instructions are compiled into host instructions usi
Autor:
Nen-Fu Huang, Wen-Yen Tsai
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 27:1783-1795
Interrupt affinitization of multi-queue network interface cards is a fundamental composition that defines how packets from individual queue are processed by which CPU-cores on multi-core platforms. In this paper, we propose qcAffin to attain an optim
Publikováno v:
Journal of Computing Science and Engineering. 9:108-117
Interrupt handling is generally separated from process scheduling. This can lead to a scheduling anomaly and priority inversion. The processor can interrupt a higher priority process that is currently executing, in order to handle a network packet re
Publikováno v:
PLOS@SOSP
In this paper we address the problem of correctly configuring interrupts. The interrupt subsystem of a computer is increasingly complex: a zoo of different controllers with varying constraints and capabilities form a network with limited connectivity
Publikováno v:
International Journal of Information and Communication Technology. 17:107
This paper proposed an interrupt handler with a time slice, which is enabled to complete the executing sections of low priority interrupt within the time period of the time slice. This method could not only reduce the numbers of interrupt threads rot
Autor:
Hee-Dong Park
Publikováno v:
International Journal of Multimedia and Ubiquitous Engineering. 9:157-164
The maskless lithography technology requires the management and transmission of exposure data at very high data rates. To meet these requirements, there were techniques on lossless data compression and on high performance data transmission. Many appl