Zobrazeno 1 - 10
of 50
pro vyhledávání: '"Interconnect topology"'
Autor:
Brian Joseph d'Auriol
Publikováno v:
ETRI Journal, Vol 39, Iss 5, Pp 632-642 (2017)
Digital all‐optical parallel computing is an important research direction and spans conventional devices and convergent nano‐optics deployments. Optical bus‐based interconnects provide interesting aspects such as relative information communicat
Externí odkaz:
https://doaj.org/article/7eb35fdf21be4fc1a6e7df0ddccca764
Publikováno v:
The Journal of Physical Chemistry C. 125:24196-24210
Akademický článek
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Publikováno v:
Journal of Parallel and Distributed Computing. 96:12-26
To realize the full potential of a high-performance computing system with a reconfigurable interconnect, there is a need to design algorithms for computing a topology that will allow for a high-throughput load distribution, while simultaneously parti
Publikováno v:
CCGrid
The recent interconnect topology designs for High Performance Computing (HPC) systems have followed two directions, one characterized by low diameter and the other by high path diversity. The low diameter design focuses on building large networks wit
Publikováno v:
ReConFig
Prototyping using multi-FPGA systems offers significant advantages over simulation and emulation based pre-silicon verification techniques in terms of performance and real world testing experience. Inter-FPGA routing interconnect and the quality of a
Publikováno v:
Hot Interconnects
The Cray Cascade architecture uses Dragonfly as its interconnect topology and employs a globally adaptive routing scheme called UGAL. UGAL directs traffic based on link loads but may make inappropriate adaptive routing decisions in various situations
Publikováno v:
IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15)
IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), Apr 2015, Naples, Italy. pp.1-6
DTIS
IEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), Apr 2015, Naples, Italy. pp.1-6
DTIS
International audience; This paper presents a BIST scheme for a new hierarchical interconnect topology in mesh FPGAs. The proposed technique ensures full test and diagnosis by performing selection of test paths. It uses 2×2 adjacent logic resources.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c6a88bfdc3ec874f3515b691d59a6a26
https://hal.archives-ouvertes.fr/hal-01400596
https://hal.archives-ouvertes.fr/hal-01400596
Publikováno v:
Journal of Japan Institute of Electronics Packaging. 5:342-348
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2014, 33 (4), pp.599-612. ⟨10.1109/TCAD.2013.2292510⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014, 33 (4), pp.599-612. ⟨10.1109/TCAD.2013.2292510⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2014, 33 (4), pp.599-612. ⟨10.1109/TCAD.2013.2292510⟩
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014, 33 (4), pp.599-612. ⟨10.1109/TCAD.2013.2292510⟩
International audience; The problem of accuracy evaluation is one of the most time consuming tasks during the fixed-point refinement process. Analytical techniques based on perturbation theory have been proposed in order to overcome the need for long
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4dc00fc5415a9adc0f3d4ba9386d7b4a
https://hal.inria.fr/hal-01097606/document
https://hal.inria.fr/hal-01097606/document