Zobrazeno 1 - 10
of 350
pro vyhledávání: '"Interconnect technology"'
Publikováno v:
FttX. Sep2018, Vol. 30 Issue 9, p4-5. 2p.
Publikováno v:
IEEE Transactions on Electron Devices, vol 68, iss 4
Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increa
Akademický článek
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Autor:
Nies, Cara-Lena
Copper interconnects will struggle to keep up with the advances in transistor miniaturisation. This creates a significant limiting factor in trying to keep Moore’s Law on track into the 2020’s. At smaller dimensions, Cu prefers to form non-conduc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=od______1535::b39de1da775bc1ef030ebaec1250878d
https://hdl.handle.net/10468/14106
https://hdl.handle.net/10468/14106
Publikováno v:
2021 18th International SoC Design Conference (ISOCC).
Autor:
Baklanov, Mikhail R., Maex, Karen
Publikováno v:
Philosophical Transactions: Mathematical, Physical and Engineering Sciences, 2006 Jan . 364(1838), 201-215.
Externí odkaz:
https://www.jstor.org/stable/25190180
Autor:
Loh, John
Publikováno v:
Global Capital. 7/25/2016, Issue 1464, p72-72. 1p.
Autor:
M.H. Lee, Winston Shue
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
This paper examines the challenges facing current copper damascene interconnect and the possible technologies to extend it. In addition, various novel materials are reviewed for their potential application in future interconnect.
Publikováno v:
2020 21st International Conference on Electronic Packaging Technology (ICEPT).
Wire bonding was still the most popular interconnect technology in the first-level packaging. In fine pitch packaging, Au-Au bonding system was preferred, and had a higher reliability, which was widely used in consumer and military products. The qual
Publikováno v:
VTS
Many semi-conductor manufacturing companies use 3D interconnect technology to flexibly combine smaller heterogeneous designs in a system-on-package. Internal I/O (IIO) are placed at two ends of the inter-die interconnect. Small dimension of IIOs proh