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pro vyhledávání: '"Instruction set simulator"'
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Publikováno v:
VLSI-SoC
Metamorphic Testing (MT) has been shown to be a very effective technique in the Software (SW) domain. MT does not require a reference model to compare against for testing but instead relies on Metamorphic Relations (MR) to derive the expected result
Publikováno v:
2021 International Conference on Electronic Information Engineering and Computer Science (EIECS).
Instruction set simulator is a critical tool for both architecture exploration and design of software. With the development of embedded system, a more complex software platform is required. An instruction set simulator specific to micro-controller wi
Publikováno v:
EWDTS
The microprocessor architecture simulation tools play a fundamental role in assessing the value of the new developers’ ideas in different areas of microarchitectural design such as in evaluating the performance of the entire system; in understandin
Autor:
Subhasish Mitra, Maha Kooli, J.-P. Noel, R. Gauchi, Bastien Giraud, V. Egloff, Henri-Pierre Charles, Pascal Vivet
Publikováno v:
ISLPED 2020: ACM/IEEE International Symposium on Low Power Electronics and Design
ISLPED 2020: ACM/IEEE International Symposium on Low Power Electronics and Design, Aug 2020, Boston, MA, United States. pp.121-126, ⟨10.1145/3370748.3406550⟩
ISLPED
ISLPED 2020: ACM/IEEE International Symposium on Low Power Electronics and Design, Aug 2020, Boston, MA, United States. pp.121-126, ⟨10.1145/3370748.3406550⟩
ISLPED
International audience; For big data applications, bringing computation to the memory is expected to reduce drastically data transfers, which can be done using recent concepts of Computing-In-Memory (CIM). To address kernels with larger memory data s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::49b436799d51bda6834a2519802d1bbc
https://cea.hal.science/cea-02963719/document
https://cea.hal.science/cea-02963719/document
Publikováno v:
Труды Института системного программирования РАН, Vol 31, Iss 3, Pp 47-58 (2019)
Software simulation is of a big importance during development of processors as they provide access to hardware under development. Cycle-accurate simulators allow software engineers to design and optimize high-performance algorithms and programs with
Publikováno v:
ISQED
The dawn of quantum computers threatens the security guarantees of classical public-key cryptography. This gave rise to a new class of so-called quantum-resistant cryptography algorithms and a need to efficiently implement them on embedded hardware p
Publikováno v:
DATE
In this paper we propose an effective methodology for integrating Concolic Testing (CT) with SystemC-based Virtual Prototypes (VPs) for verification of embedded SW binaries. Our methodology involves three steps: 1) integrating CT support with the Ins
Publikováno v:
ICCD
Recently, Virtual Prototypes (VPs) were introduced for the emerging RISC-V Instruction Set Architecture (ISA) and become an important part of the growing RISC-V ecosystem. A central component of the VP is the Instruction Set Simulator (ISS). VPs shou
Publikováno v:
FDL
Extensive processor verification at the Register-Transfer Level (RTL) is crucial to avoid bugs. Therefore, simulation-based approaches are prevalent but they require efficient test generation methods to achieve a thorough verification. In this paper