Výsledky vyhledávání - "Injection-Locked Clock and Data Recovery (ILCDR)"

Akademický článek

A Low Power Injection-Locked CDR Using 28 nm FDSOI Technology for Burst-Mode Applications

Autor: Yuqing Mao, Yoann Charlon, Yves Leduc, Gilles Jacquemod

Publikováno v: Journal of Low Power Electronics and Applications, Vol 14, Iss 2, p 22 (2024)

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables t

Externí odkaz: https://doaj.org/article/a510b02b0e5e4c3395ef0f9adb75b793

Zobrazit plný text záznamu

Akademický článek

Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.

Conference

Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.

Akademický článek

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology.

Autor: Choo, Min-Seong, Park, Kwanseo, Ko, Han-Gon, Cho, Sung-Yong, Lee, Kwangho, Jeong, Deog-Kyoon

Publikováno v: IEEE Journal of Solid-State Circuits; Oct2019, Vol. 54 Issue 10, p2812-2822, 11p

Zobrazit plný text záznamu

A low power injection-locked CDR using 28 nm FDSOI technology for burst-mode applications

Autor: Yuqing Mao, Yoann Charlon, Gilles Jacquemod, Yves Leduc

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using 28 nm FDSOI technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors allows us to create a QRO (Quadrature Ring Oscillator) reducing both size and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::be010226d71475a96f8d3c273aae3147
https://doi.org/10.21203/rs.3.rs-2084207/v1

Zobrazit plný text záznamu

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

Autor: Kwanseo Park, Min-Seong Choo, Deog-Kyoon Jeong, Kwangho Lee, Han-Gon Ko, Sung-Yong Cho

Publikováno v: IEEE Journal of Solid-State Circuits. 54:2812-2822

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit half-rate all-digital injection-locked clock and data recovery (ILCDR) with a path mismatch tracking (PMT) loop is presented. When injection timing is not perfectly aligned with the phase of the oscillator, the timing

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::79313bf2cb52a1d033abf622424fa1eb
https://doi.org/10.1109/jssc.2019.2917833

Zobrazit plný text záznamu

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop

Autor: Min-Seong Choo, Sung-Yong Cho, Kwangho Lee, Han-Gon Ko, Deog-Kyoon Jeong

Publikováno v: A-SSCC

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit half-rate all-digital injection-locked clock and data recovery (ILCDR) with a path mismatch tracking (PMT) loop is presented. When injection timing is not perfectly matched with the local oscillator, the timing margin

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::88a548650fc6d507ea07b3ce2ec0335b
https://doi.org/10.1109/asscc.2018.8579270

Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání