Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Indranil Hatai"'
Autor:
Indranil Hatai, Indrajit Chakrabarti
Publikováno v:
International Journal of Reconfigurable Computing, Vol 2011 (2011)
This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overa
Externí odkaz:
https://doaj.org/article/58b67e04f631439ba9364c1a29119b16
Autor:
Sibendu Samanta, Sharmila Arun Babu, T. Arun Babu, Radek Martinek, Rene Jaros, Indranil Hatai, RADHA ABBURI
This work utilizes a wearable phonocardiogram belt for acquiring signals from remote areas. Four sequential methodologies are undergone in the proposed work for resilience, and effectiveness. Intelligent, and accurate FHR monitoring. At first, the no
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1f491874040ca13af73bcce5760c8702
https://doi.org/10.36227/techrxiv.22561735.v2
https://doi.org/10.36227/techrxiv.22561735.v2
Epilepsy is a neurological condition that distresses millions of individuals throughout the world. The lives of epileptic patients are greatly influenced by the early detection of impending seizures. In this paper, Design an Efficient FPGA Based Hard
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ff48ada7f4ba228690f68aa98d47a92
https://doi.org/10.21203/rs.3.rs-1819772/v1
https://doi.org/10.21203/rs.3.rs-1819772/v1
Publikováno v:
Multimedia Tools and Applications.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12af1444b23ab829daeb62cea3b085d2
https://doi.org/10.1007/s11042-023-14699-1
https://doi.org/10.1007/s11042-023-14699-1
Publikováno v:
2021 2nd International Conference on Communication, Computing and Industry 4.0 (C2I4).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::987f0ef8b3b7e779620e5d3e075afcba
https://doi.org/10.1109/c2i454156.2021.9689307
https://doi.org/10.1109/c2i454156.2021.9689307
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:130-140
This paper introduces a computationally efficient hardware architecture for reconfigurable multiple constant multiplication block, which functions according to the canonical signed digit (CSD)-based vertical and horizontal common sub-expression elimi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c9265fd5ef69e4f453e1365f2b43f76
https://doi.org/10.1109/tcsi.2017.2719053
https://doi.org/10.1109/tcsi.2017.2719053
Autor:
Annapurna Mondal, Sagnik Bhar, Indranil Hatai, Hafizur Rahaman, Kasturi Ghosh, Supriyo Srimani
Publikováno v:
2019 IEEE Region 10 Symposium (TENSYMP).
In biomedical applications, a sigma-delta analog-to-digital converter (SDADC), due to its high resolution, is very important in data acquisition systems. A decimator is used in SDADC to control the output sample rate. It also acts as a low pass filte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9d610c2f6fa96075517e97b942ec2be
https://doi.org/10.1109/tensymp46218.2019.8971138
https://doi.org/10.1109/tensymp46218.2019.8971138
Autor:
Supriyo Srimani, Subhajit Das, Annapurna Mondal, Indranil Hatai, Sagnik Bhar, Hafizur Rahaman, Kasturi Ghosh
Publikováno v:
ISDCS
A driver circuit of an analog-to-digital converter (ADC) is one of the critical parts which influences the transient response, frequency response and the noise floor of the system. To satisfy the accuracy and speed requirements, a modified differenti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ab9b2fdae6a612599e9e76fc2596c1c
https://doi.org/10.1109/isdcs.2019.8719267
https://doi.org/10.1109/isdcs.2019.8719267
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:1150-1154
This brief proposes a two-step optimization technique for designing a reconfigurable VLSI architecture of an interpolation filter for multistandard digital up converter (DUC) to reduce the power and area consumption. The proposed technique initially
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::451645130ec2ef62079475a7e217ead8
https://doi.org/10.1109/tvlsi.2014.2321171
https://doi.org/10.1109/tvlsi.2014.2321171
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. :1-10
This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dyna
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00136fa625c9c6759579d05a116a2033
https://doi.org/10.1109/tcsi.2015.2388838
https://doi.org/10.1109/tcsi.2015.2388838